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? 2011 freescale semiconductor, inc. all rights reserved. freescale semiconductor technical data this document contains deta iled information about power considerations, dc/ac electrical characteristics, and ac timing specifications for .13m (hip7) members of the powerquicc ii family of integrated communications processors?the mpc8272, the mpc8248, the mpc8271, and the mpc8247. they include on a single chip a 32-bit power architecture? core that incorporates memory management units (mmus) and instruction and data caches and that implements the power architecture instruction set; a modified communications processor module (cpm); and an integrated security engine (sec) for encryption (the mpc8272 and the mpc8248 only). all four devices are collectively referred to throughout this hardware specification as ?the mpc8272? unless otherwise noted. document number: mpc8272ec rev. 3, 09/2011 contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . 7 3. dc electrical characteristics . . . . . . . . . . . . . . . . . . . 9 4. thermal characteristics . . . . . . . . . . . . . . . . . . . . . . 14 5. power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6. ac electrical characteristics . . . . . . . . . . . . . . . . . . 18 7. clock configuration modes . . . . . . . . . . . . . . . . . . . 27 8. pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9. package description . . . . . . . . . . . . . . . . . . . . . . . . . 56 10. ordering information . . . . . . . . . . . . . . . . . . . . . . . . 58 11. document revision history . . . . . . . . . . . . . . . . . . . 58 mpc8272 powerquicc ii family hardware specifications
mpc8272 powerquicc ii family hardware specifications, rev. 3 2 freescale semiconductor overview 1overview this table shows the functionality supported by each soc in the mpc8272 family. devices in the mpc8272 family are available in two packages?the vr or zq package?as shown in . for package ordering information, see section 10, ?ordering information.? table 1. mpc8272 powerquicc ii family functionality functionality socs mpc8272 mpc8248 mpc8271 mpc8247 package 1 1 see ta b l e 2 . 516 pbga serial communications controllers (sccs) 3333 quicc multi-channel controller (qmc) yes yes yes yes fast communication controllers (fccs) 2222 i-cache (kbyte) 16 16 16 16 d-cache (kbyte) 16 16 16 16 ethernet (10/100) 2222 utopia ii ports 1010 multi-channel controllers (mccs) 0000 pci bridge yes yes yes yes transmission convergence (tc) layer ???? inverse multiplexing for atm (ima) ???? universal serial bus (usb) 2.0 full/low rate 1111 security engine (sec) yes yes ? ? table 2. mpc8272 powerquicc ii device packages code (package) vr (516 pbga?lead free) zq (516 pbga?lead spheres) device mpc8272vr mpc8272zq mpc8248vr mpc8248zq mpc8271vr mpc8271zq mpc8247vr mpc8247zq
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 3 overview this figure shows the block diagram of the soc. figure 1. soc block diagram 1.1 features the major features of the soc are as follows: ? dual-issue integer (g2_le) core ? a core version of the mpc603e microprocessor ? system core microprocessor s upporting frequencies of 266?400 mhz ? separate 16 kb data and instruction caches: ? four-way set associative ? physically addressed ? lru replacement algorithm ? power architecture?-compliant memory management unit (mmu) ? common on-chip processor (cop) test interface ? supports bus snooping for cache coherency 16 kb g2_le core i-cache i-mmu 16 kb d-cache d-mmu communication processor module (cpm) timers parallel i/o baud rate generators 32-bit risc microcontroller and program rom serial dma 60x-to-pci bridge memory controller clock counter system functions system interface unit (siu) pci bus 32 bits, up to 66 mhz fcc1 fcc2 scc1 scc3 scc4 smc1 smc2 spi i 2 c serial interface 2 mii/rmii port ports 60x bus interrupt controller time slot assigner 2 tdm ports non-multiplexed i/o bus interface unit virtual idmas 16 kb security (sec)1 2 1 8-bit utopia serial interface 4 kb instruction ram data ram notes: 1 mpc8272/8248 only 2 mpc8272/8271 only usb 2.0
mpc8272 powerquicc ii family hardware specifications, rev. 3 4 freescale semiconductor overview ? floating-point unit (fpu) supports floating-point arithmetic ? support for cache locking ? low-power consumption ? separate power supply for internal logic (1.5 v) and for i/o (3.3 v) ? separate plls for g2_le core and for the communications processor module (cpm) ? g2_le core and cpm can run at different frequencies for power/performance optimization ? internal core/bus clock multiplier that provides ratios 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 5.5:1, 6:1, 7:1, 8:1 ? internal cpm/bus clock multiplier that provides ratios 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1, 8:1 ratios ? 64-bit data and 32-bit address 60x bus ? bus supports multiple master designs?up to two external masters ? supports single transfers and burst transfers ? 64-, 32-, 16-, and 8-bit port sizes c ontrolled by on-chip memory controller ? 60x-to-pci bridge ? programmable host bridge and agent ? 32-bit data bus, 66 mhz, 3.3 v ? synchronous and asynchronous 60x and pci clock modes ? all internal address space available to external pci host ? dma for memory block transfers ? pci-to-60x address remapping ? system interface unit (siu) ? clock synthesizer ? reset controller ? real-time clock (rtc) register ? periodic interrupt timer ? hardware bus monitor and software watchdog timer ? ieee 1149.1 jtag test access port ? eight bank memory controller ? glueless interface to sram, page mode sdram, dram, eprom, flash, and other user-definable peripherals ? byte write enables ? 32-bit address decodes with programmable bank size ? three user-programmable machines, general-pur pose chip-select machine, and page mode pipeline sdram machine ? byte selects for 64-bit bus width (60x) ? dedicated interface logic for sdram ? disable cpu mode
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 5 overview ? integrated security engine (sec) (mpc8272 and mpc8248 only) ? supports des, 3des, md-5, sha-1, aes, pkeu, rng and rc-4 encryption algorithms in hardware ? communications processor module (cpm) ? embedded 32-bit communications processor (cp) uses a risc architecture for flexible support for communications peripherals ? interfaces to g2_le core through on-chip dual-port ram and dma controller. (dual-port ram size is 16 kb plus 4 kb dedicated instruction ram.) ? microcode tracing capabilities ? eight cpm trap registers ? universal serial bus (usb) controller ? supports usb 2.0 full/low rate compatible ? usb host mode ? supports control, bulk, interrupt, and isochronous data transfers ? crc16 generation and checking ? nrzi encoding/decoding with bit stuffing ? supports both 12- and 1.5-mbps data rates (a utomatic generation of preamble token and data rate configuration). note that low-speed operation requires an external hub. ? flexible data buffers with multiple buffers per frame ? supports local loopback mode for diagnostics (12 mbps only) ? supports usb slave mode ? four independent endpoints support control, bulk, interrupt, and isochronous data transfers ? crc16 generation and checking ? crc5 checking ? nrzi encoding/decoding with bit stuffing ? 12- or 1.5-mbps data rate ? flexible data buffers with multiple buffers per frame ? automatic retransmission upon transmit error ? serial dma channels for receive and transmit on all serial channels ? parallel i/o registers with open-drain and interrupt capability ? virtual dma functionality executing memory-to-memory and memory-to-i/o transfers ? two fast communication controllers (fccs) supporting the following protocols: ? 10-/100-mbit ethernet/ieee 802.3 cdma/c s interface through media independent interface (mii) ? transparent ? hdlc?up to t3 rates (clear channel)
mpc8272 powerquicc ii family hardware specifications, rev. 3 6 freescale semiconductor overview ? one of the fccs supports atm (mpc8272 and mpc8271 only)?full-duplex sar at 155 mbps, 8-bit utopia interface 31 mphys, aal5, aal1, aal2, aal0 protocols, tm 4.0 cbr, vbr, ubr, abr traffic types, up to 64-k external connections ? three serial communications controllers (sccs) identical to those on the mpc860 supporting the digital portions of the following protocols: ? ethernet/ieee 802.3 cdma/cs ? hdlc/sdlc and hdlc bus ? universal asynchronous receiver transmitter (uart) ? synchronous uart ? binary synchronous (bisync) communications ? transparent ? quicc multichannel controlle r (qmc) up to 64 channels ? independent transmit and receive routing, frame synchronization. ? serial-multiplexed (full-duplex) input/output 2048, 1544, and 1536 kbps pcm highways ? compatible with t1/ds1 24-channel and cept e1 32-channel pcm highway, isdn basic rate, isdn primary rate, and user defined. ? subchanneling on each time slot. ? independent transmit and receive routi ng, frame synchronization and clocking ? concatenation of any not necessarily consecutive time slots to channels independently for receiver/transmitter ? supports h1,h11, and h12 channels ? allows dynamic allocation of channels ? scc3 in nmsi mode is not usable when usb is enabled. ? two serial management controllers (smcs), identical to those of the mpc860 ? provides management for bri devices as gene ral-circuit interface (gci) controllers in time-division-multiplexed (tdm) channels ? transparent ? uart (low-speed operation) ? one serial peripheral interface identical to the mpc860 spi ? one i 2 c controller (identical to the mpc860 i 2 c controller) ? microwire compatible ? multiple-master, single-master, and slave modes ? up to two tdm interfaces ? supports one group s of two tdm channels ? 1024 bytes of si ram ? eight independent baud rate generators and 14 input clock pins for supplying clocks to fcc, scc, smc, and usb serial channels ? four independent 16-bit timers that can be interconnected as two 32-bit timers
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 7 operating conditions ? pci bridge ? pci specification revision 2.2-compliant and supports frequencies up to 66 mhz ? on-chip arbitration ? support for pci to 60x memory and 60x memory to pci streaming ? pci host bridge or peripheral capabilities ? includes four dma channels for the following transfers: ? pci-to-60x to 60x-to-pci ? 60x-to-pci to pci-to-60x ? pci-to-60x to pci-to-60x ? 60x-to-pci to 60x-to-pci ? includes the configuration registers required by the pci standard (which are automatically loaded from the eprom to configure the mpc8272) and message and doorbell registers ? supports the i 2 o standard ? hot-swap friendly (supports the hot swap sp ecification as defined by picmg 2.1 r1.0 august 3, 1998) ? support for 66 mhz, 3.3 v specification ? 60x-pci bus core logic, which uses a buffer pool to allocate buffers for each port 2 operating conditions this table shows the maximum electrical ratings. table 3. absolute maximum ratings 1 1 absolute maximum ratings are stress ratings only; functional operation (see ta ble 4 ) at the maximums is not guaranteed. stress beyond those listed may affect device reliability or cause permanent damage. rating symbol value unit core supply voltage 2 2 caution: vdd/vccsyn must not exceed vddh by more than 0.4 v during normal operation. it is recommended that vdd/vccsyn should be raised before or simultaneous with vddh during power-on reset. vdd/vccsyn may exceed vddh by more than 0.4 v during power-on reset for no more than 100 ms. vdd ?0.3 ? 2.25 v pll supply voltage 2 vccsyn ?0.3 ? 2.25 v i/o supply voltage 3 3 caution: vddh can exceed vdd/vccsyn by 3.3 v during power on reset by no more than 100 msec. vddh should not exceed vdd/vccsyn by more than 2.5 v during normal operation. vddh ?0.3 ? 4.0 v input voltage 4 4 caution: vin must not exceed vddh by more than 2.5 v at any time, including during power-on reset. vin gnd(?0.3) ? 3.6 v junction temperature t j 120 c storage temperature range t stg (?55) ? (+150) c
mpc8272 powerquicc ii family hardware specifications, rev. 3 8 freescale semiconductor operating conditions this table lists recommended operational voltage conditions. this soc contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be take n to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circ uit. reliability of operation is enhanced if unused inputs are tied to an appropriate l ogic voltage level (either gnd or v cc ). this figure shows the undershoot and overshoot voltage of the 60x bus memory interface of the soc. note that in pci mode the i/o interface is different. figure 2. overshoot/undershoot voltage table 4. recommended operating conditions 1 1 caution: these are the recommended and tested operating conditions. proper operation outside of these conditions is not guaranteed. rating symbol value unit core supply voltage vdd 1.425 ? 575 v pll supply voltage vccsyn 1.425 ? 575 v i/o supply voltage vddh 3.135 ? 3.465 v input voltage vin gnd (?0.3) ? 3.465 v junction temperature (maximum) t j 105 2 2 note that for extended temperature parts the range is (-40) t a ? 105 t j . c ambient temperature t a 0?70 2 c gnd gnd ? 0.3 v gnd ? 1.0 v not to exceed 10% gv dd of t sdram_clk gv dd + 5% 4 v v ih v il
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 9 dc electrical characteristics 3 dc electrical characteristics this table shows dc electrical characteristics. table 5. dc electrical characteristics 1 characteristic symbol min max unit input high voltage?all inputs except tck, trst and poreset 2 v ih 2.0 3.465 v input low voltage 3 v il gnd 0.8 v clkin input high voltage v ihc 2.4 3.465 v clkin input low voltage v ilc gnd 0.4 v input leakage current, v in = vddh 4 i in ?10a hi-z (off state) leakage current, v in = vddh 2 i oz ?10a signal low input current, v il = 0.8 v i l ?1a signal high input current, v ih = 2.0 v i h ?1a output high voltage, i oh = ?2 ma except utopia mode, and open drain pins in utopia mode 5 (utopia pins only): i oh = -8.0ma pa[8?31] pb[18?31] pc[0?1,4?29] pd[7?25, 29?31] v oh 2.4 ? v in utopia mode 5 (utopia pins only): i ol = 8.0ma pa[8?31] pb[18?31] pc[0?1,4?29] pd[7?25, 29?31] v ol ?0.5v
mpc8272 powerquicc ii family hardware specifications, rev. 3 10 freescale semiconductor dc electrical characteristics i ol = 6.0ma br bg /irq6 abb /irq2 ts a[0-31] tt[0-4] tbst tsize[0?3] aack artry dbg /irq7 dbb /irq3 d[0?63] irq3 /ckstp_out /e xt_br3 irq4 /core_sreset /ext_bg3 irq5 /tben /ext_dbg3 /c int psdval ta tea gbl /irq1 ci/ baddr29/irq2 wt /baddr30/irq3 baddr31/irq5 /cin t c pu_br /int_out irq0 /nmi_out poreset /pci_rst hreset sreset rstconf v ol ?0.4v table 5. dc electrical characteristics 1 (continued) characteristic symbol min max unit
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 11 dc electrical characteristics i ol = 5.3ma c s [0?5] cs6 /bctl1 /smi cs7 /tlbsync baddr27/ irq1 baddr28/ irq2 ale/ irq4 bctl0 pwe [0?7]/psddqm [0?7]/pbs [0?7] psda10/pgpl0 psdwe/ pgpl1 poe /psdras /pgpl2 psdcas/pgpl3 pgta /pupmwait/pgpl4 psdamux/pgpl5 pci_cfg0 ( pci_host_en ) pci_cfg1 ( pci_arb_en ) pci_cfg2 ( dll_enable) modck1/rsrv /tc(0)/bnksel(0) modck2/cse0/tc(1)/bnksel(1) modck3cse1/tc(2)/bnksel(2) i ol = 3.2ma pci_par pci_frame pci_trdy pci_irdy pci_stop pci_devsel pci_idsel pci_perr pci_serr pci_req0 pci_req1 / cpi_hs_es pci_gnt0 pci_gnt1 / cpi_hs_les pci_gnt2 / cpi_hs_enum pci_rst pci_inta pci_req2 dllout pci_ad(0-31) pci_c (0?3)/b e (0-3) pa[8?31] pb[18?31] pc[0?1,4?29] pd[7?25, 29?31] tdo v ol ?0.4v 1 the default configuration of the cpm pins (pa[8?31], pb[18?31], pc[0?1,4?29], pd[7?25, 29?31]) is input. to prevent excessive dc current, it is recommended either to pull unused pins to gnd or vddh, or to configure them as outputs. 2 tck, trst and poreset have min vih = 2.5v. 3 v il for iic interface does not match iic standard, but does meet iic standard for v ol and should not cause any compatibility issue. 4 the leakage current is measured for nominal vddh,vccsyn, and vdd. table 5. dc electrical characteristics 1 (continued) characteristic symbol min max unit
mpc8272 powerquicc ii family hardware specifications, rev. 3 12 freescale semiconductor dc electrical characteristics 5 mpc8272 and mpc8271 only. table 6. characteristic symbol min max unit input high voltage?all inputs except tck, trst and poreset 1 v ih 2.0 3.465 v input low voltage v il gnd 0.8 v clkin input high voltage v ihc 2.4 3.465 v clkin input low voltage v ilc gnd 0.4 v input leakage current, v in = vddh 2 i in ?10a hi-z (off state) leakage current, v in = vddh 2 i oz ?10a signal low input current, v il = 0.8 v 3 i l ?1a signal high input current, v ih = 2.0 v i h ?1a output high voltage, i oh = ?2 ma except utopia mode, and open drain pins in utopia mode 4 (utopia pins only): i oh = -8.0ma v oh 2.4 ? v in utopia mode 4 (utopia pins only): i ol = 8.0ma v ol ?0.5v i ol = 6.0ma br bg abb /irq2 ts a[0-31] tt[0-4] tbst tsize[0?3] aack artry dbg dbb /irq3 d[0-63] //ext_br3 //ext_bg3 /tben /ext_dbg3 /cint psdval ta tea gbl /irq1 ci/ baddr29/irq2 wt /baddr30/irq3 baddr31/irq5 /cint cpu_br irq0 /nmi_out /pci_rst hreset sreset rstconf v ol ?0.4v
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 13 dc electrical characteristics i ol = 5.3ma c s [0-9] cs (10)/bctl1 cs (11)/ap(0) baddr[27?28] ale bctl0 pwe [0?7]/psddqm [0?7]/pbs [0?7] psda10/pgpl0 psdwe/ pgpl1 poe /psdras /pgpl2 psdcas/pgpl3 pgta /pupmwait/pgpl4/ppbs psdamux/pgpl5 lwe [0?3]lsddqm [0?3]/lbs [0?3]/pci_cfg[0?3] lsda10/lgpl0/pci_modckh0 lsdwe/lgpl1/pci_modckh1 loe /lsdras /lgpl2/pci_modckh2 lsdcas/lgpl3/pci_modckh3 lgta/lupmwait/lgpl4/lpbs lsdamux/lgpl5/pci_modck lwr modck[1?3]/ap[1?3]/tc[0?2]/bnksel[0?2] i ol = 3.2ma l_a14/par l_a15/frame /smi l_a16/trdy l_a17/irdy /ckstp_out l_a18/stop l_a19/devsel l_a20/idsel l_a21/perr l_a22/serr l_a23/req0 l_a24/req1/hsejsw l_a25/gnt0 l_a26/gnt1/hsled l_a27/gnt2/hsenum l_a28/rst /core_sreset l_a29/inta l_a30/req2 l_a31 lcl_d[0-31)]/ad[0-31] lcl_dp[03]/c/be [0-3] pa[0?31] pb[4?31] pc[0?31] pd[4?31] tdo qreq v ol ?0.4v 1 tck, trst and poreset have min vih = 2.5v. 2 the leakage current is measured for nominal vddh,vccsyn, and vdd. 3 v il for iic interface does not match iic standard, but does meet iic standard for v ol and should not cause any compatibility issue. table 6. characteristic symbol min max unit
mpc8272 powerquicc ii family hardware specifications, rev. 3 14 freescale semiconductor thermal characteristics 4 thermal characteristics this table describes thermal characteristics. see table 2 for information on a given soc?s package. discussions of each characteristic are provided in section 4.1, ?estimation with junction-to-ambient thermal resistance ,? through section 4.7, ?references .? for the these discussions, p d =(v dd i dd ) + pi/o, where pi/o is the power dissipation of the i/o drivers. 4.1 estimation with junction-to-ambient thermal resistance an estimation of the chip junction temperature, t j , in c can be obtained from the following equation: t j = t a + (r ja p d ) where: t a = ambient temperature (oc) r ja = package junction-to-ambient thermal resistance (oc/w) p d = power dissipation in package the junction-to-ambient thermal resistance is an i ndustry standard value that provides a quick and easy estimation of thermal performance. however, the answer is only an estimate; test cases have demonstrated that errors of a factor of two (in the quantity t j ? t a ) are possible. 4 mpc8280, mpc8275vr, mpc8275zq only. table 7. thermal characteristics characteristic symbol value unit air flow junction-to-ambient? single-layer board 1 1 assumes no thermal vias r ja 27 c/w natural convection 21 1 m/s junction-to-ambient? four-layer board r ja 19 c/w natural convection 16 1 m/s junction-to-board 2 2 thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. r jb 11 c/w ? junction-to-case 3 3 thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). r jc 8 c/w ? junction-to-package top 4 4 thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt. r jt 2 c/w ?
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 15 thermal characteristics 4.2 estimation with junction-to-case thermal resistance historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: r ja = r jc + r ca where: r ja = junction-to-ambient thermal resistance (oc/w) r jc = junction-to-case thermal resistance (oc/w) r ca = case-to-ambient thermal resistance (oc/w) r jc is device related and cannot be influenced by the user. the user adjusts the thermal environment to affect the case-to-ambient thermal resistance, r ca . for instance, the user can change the air flow around the device, add a heat sink, change the mounting arra ngement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. this thermal model is most useful for ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink to the ambient environment. for most packages, a better model is required. 4.3 estimation with junction-to-board thermal resistance a simple package thermal model which has dem onstrated reasonable accuracy (about 20%) is a two-resistor model consisting of a junction-to-boa rd and a junction-to-case thermal resistance. the junction-to-case thermal resistance covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package. the junction-to-board thermal resistance describes the thermal performance when most of the h eat is conducted to the prin ted circuit board. it has been observed that the thermal performance of most plastic packages, especially pbga packages, is strongly dependent on the board temperature. if the board temperature is known, an estimate of the junction temperature in the environment can be made using the following equation: t j = t b + (r jb p d ) where: r jb = junction-to-board thermal resistance (oc/w) t b = board temperature (oc) p d = power dissipation in package if the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. for this method to work, the board and board mounting must be similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a power and a ground plan e) and by attaching the thermal balls to the ground plane.
mpc8272 powerquicc ii family hardware specifications, rev. 3 16 freescale semiconductor thermal characteristics 4.4 estimation using simulation when the board temperature is not known, a thermal s imulation of the application is needed. the simple two-resistor model can be used with the thermal simulation of the application, or a more accurate and complex model of the package can be used in the thermal simulation. 4.5 experimental determination to determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter ( jt ) can be used to determine the junction temperature with a measurement of the temperature at the top cente r of the package case using the following equation: t j = t t + ( jt p d ) where: jt = thermal characterization parameter t t = thermocouple temperature on top of package p d = power dissipation in package the thermal characterization parameter is measured per jedec jesd51-2 specification using a 40-gauge type t thermocouple epoxied to the top center of th e package case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple junction and over 1 mm of wire extendi ng from the junction. the thermocouple wire is placed flat against the case to a void measurement errors caused by c ooling effects of the thermocouple wire. 4.6 layout practices each vdd and vddh pin should be provided with a lo w-impedance path to the board?s power supplies. each ground pin should likewise be provided with a low-impedance path to ground. the power supply pins drive distinct groups of logic on chip. the vdd and vddh power supplies should be bypassed to ground using bypass capacitors located as close as possible to the four sides of the package. for filtering high frequency noise, a capacitor of 0.1uf on each vdd a nd vddh pin is recommended. further, for medium frequency noise, a total of 2 capacitors of 47uf fo r vdd and 2 capacitors of 47uf for vddh are also recommended. the capacitor leads and associated printed circuit traces connecting to chip vdd, vddh and ground should be kept to less than half an inch per capacitor lead. boards should employ separate inner layers for power and gnd planes. all output pins on the soc have fast rise and fall ti mes. printed circuit (pc) trace interconnection length should be minimized to minimize overdamped conditions and reflections caused by these fast output switching times. this recommendation particularly a pplies to the address and data buses. maximum pc trace lengths of six inches are recommended. capacita nce calculations should consider all device loads as well as parasitic capacitances due to the pc traces. attention to proper pcb la yout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the vdd and gnd circuits. pull up all unused inputs or signals that will be inputs during reset. special care should be taken to minimize the noise levels on the pll supply pins.
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 17 power dissipation 4.7 references semiconductor equipment and materi als international(415) 964-5111 805 east middlefield rd. mountain view, ca 94043 mil-spec and eia/jesd (jedec) specifications800-854-7179 or (available from global engineering documents)303-397-7956 jedec specifications http://www.jedec.org 1. c.e. triplett and b. joiner, ?an experimental characterization of a 272 pbga within an automotive engine controller module,? proceedings of semitherm, san diego, 1998, pp. 47 ? 54. 2. b. joiner and v. adams, ?measurement and simulation of junction to board thermal resistance and its application in thermal modeling,? proc eedings of semitherm, san diego, 1999, pp. 212 ? 220. 5 power dissipation this table provides preliminary, estimated power dissipat ion for various configurations. note that suitable thermal management is required to ensure the junction temperature does not exceed the maximum specified value. also note that the i/o power should be included when determining whether to use a heat sink. for a complete list of possible clock configurations, see section 7, ?clock configuration modes.? table 8. estimated power dissipation for various configurations 1 1 test temperature = 105 c bus (mhz) cpm multiplication factor cpm (mhz) cpu multiplication factor cpu (mhz) p int (w) 2,3 2 p int = i dd x v dd watts 3 values do not include i/o. add the following estimates for active i/o based on the following bus speeds: 66.7 mhz = 0.35 w (nominal), 0.4 w (maximum) 83.3 mhz = 0.4 w (nominal), 0.5 w (maximum) 100 mhz = 0.5 w (nominal), 0.6 w (maximum) 133 mhz = 0.7 w (nominal), 0.8 w (maximum) vddl 1.5 volts nominal maximum 66.67 3 200 4 266 1 1.2 100 2 200 3 300 1.1 1.3 100 2 200 4 400 1.3 1.5 133 2 267 3 400 1.5 1.8
mpc8272 powerquicc ii family hardware specifications, rev. 3 18 freescale semiconductor ac electrical characteristics 6 ac electrical characteristics the following sections include illustrations and tables of clock diagrams, signals, and cpm outputs and inputs for 66.67/83.33/100/133 mhz devices. note that ac timings are based on a 50-pf load for max delay and 10-pf load for min delay. typical out put buffer impedances are shown in this table. 6.1 cpm ac characteristics this table lists cpm output characteristics. table 9. output buffer impedances 1 1 these are typical values at 65 c. impedance may vary by 25% with process and temperature. output buffers typical impedance ( ) 60x bus 45 or 27 2 2 impedance value is selected through siumcr[20,21]. see the soc reference manual. memory controller 45 or 27 2 parallel i/o 45 pci 27 table 10. ac characteristics for cpm outputs 1 1 output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. spec number characteristic value (ns) max min maximum delay minimum delay 66 mhz 83 mhz 100 mhz 133 mhz 66 mhz 83 mhz 100 mhz 133 mhz sp36a sp37a fcc outputs?internal clock (nmsi) 6 5.5 5.5 5.5 0.5 0.5 0.5 0.5 sp36b sp37b fcc outputs?external clock (nmsi) 8 8882222 sp38a sp39a scc/smc/spi/i2c outputs?internal clock (nmsi) 10 10 10 10 0 0 0 0 sp38b sp39b scc/smc/spi/i2c outputs?external clock (nmsi) 8 8882222 sp40 sp41 tdm outputs/si 11 11 11 11 2.5 2.5 2.5 2.5 sp42 sp43 timer/idma outputs 11 11 11 11 0.5 0.5 0.5 0.5 sp42a sp43a pio outputs 11 11 11 11 0.5 0.5 0.5 0.5
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 19 ac electrical characteristics this table lists cpm input characteristics. note: rise/fall time on cpm input pins it is recommended that the rise/fall time on cpm input pins should not exceed 5 ns. this should be enforced especially on clock signals. rise time refers to signal transitions from 10% to 90% of vcc; fall time refers to transitions from 90% to 10% of vcc. note although the specifications generally refe rence the rising edge of the clock, the following ac timing diagrams also apply when the falling edge is the active edge. this figure shows the fcc internal clock. figure 3. fcc internal clock diagram table 11. ac characteristics for cpm inputs 1 1 input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. spec number characteristic value (ns) setup hold setup hold 66 mhz 83 mhz 100 mhz 133 mhz 66 mhz 83 mhz 100 mhz 133 mhz sp16a sp17a fcc inputs?internal clock (nmsi) 6 6660000 sp16b sp17b fcc inputs?external clock (nmsi) 2.5 2.5 2.5 2.5 2222 sp18a sp19a scc/smc/spi/i2c inputs?internal clock (nmsi) 6 6660000 sp18b sp19b scc/smc/spi/i2c inputs?external clock (nmsi) 4 4442222 sp20 sp21 tdm inputs/si 3 3 3 3 2.5 2.5 2.5 2.5 sp22 sp23 pio/timer/idma inputs 8 8 8 8 0.5 0.5 0.5 0.5 brg_out fcc input signals fcc output signals fcc output signals note: when gfmr.[tci] = 1 note: when gfmr[tci] = 0 sp36a/sp37a sp36a/sp37a sp17a sp16a
mpc8272 powerquicc ii family hardware specifications, rev. 3 20 freescale semiconductor ac electrical characteristics this figure shows the fcc external clock. figure 4. fcc external clock diagram this figure shows the scc/smc/spi/i 2 c external clock. figure 5. scc/smc/spi/i 2 c external clock diagram serial clkin fcc input signals fcc output signals fcc output signals note: when gfmr[tci] = 1 note: when gfmr[tci] = 0 sp16b sp17b sp36b/sp37b sp36b/sp37b serial clkin scc/smc/spi/i2c input signals scc/smc/spi/i2c output signals sp18b sp19b sp38b/sp39b (see note) (see note) note: there are four possible timing conditions for spi: 1. input sampled on the rising edge and output driven on the rising edge. 2. input sampled on the rising edge and output driven on the falling edge. 3. input sampled on the falling edge and output driven on the falling edge (shown). 4. input sampled on the falling edge and output driven on the rising edge. note: there are two possible timing conditions for scc/smc/i 2 c: 1. input sampled on the falling edge and output driven on the falling edge (shown). 2. input sampled on the falling edge and output driven on the rising edge. new clkin
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 21 ac electrical characteristics this figure shows the scc/smc/spi/i 2 c internal clock. figure 6. scc/smc/spi/i 2 c internal clock diagram this figure shows tdm input and output signals. figure 7. tdm signal diagram brg_out scc/smc/spi/i2c input signals scc/smc/spi/i2c output signals sp18a sp19a sp38a/sp39a (see note) (see note) note: there are four possible timing conditions for scc and spi: 1. input sampled on the rising edge and output driven on the rising edge (shown). 2. input sampled on the rising edge and output driven on the falling edge. 3. input sampled on the falling edge and output driven on the falling edge. 4. input sampled on the falling edge and output driven on the rising edge. serial clkin tdm input signals tdm output signals sp20 sp21 sp40/sp41 note: there are four possible tdm timing conditions: 1. input sampled on the rising edge and output driven on the rising edge (shown). 2. input sampled on the rising edge and output driven on the falling edge. 3. input sampled on the falling edge and output driven on the falling edge. 4. input sampled on the falling edge and output driven on the rising edge.
mpc8272 powerquicc ii family hardware specifications, rev. 3 22 freescale semiconductor ac electrical characteristics this figure shows pio and timer signals. figure 8. pio and timer signal diagram 6.2 siu ac characteristics this table lists siu input characteristics. note: clkin jitter and duty cycle the clkin input to the soc should not exceed +/? 150 psec of jitter (peak-to-peak). this represents total input jitter?the combination of short term (peak-to-peak) and long term (cumulative). the duty cycle of clkin should not exceed the ratio of 40:60. note: spread spectrum clocking spread spectrum clocking is allowed with 1% input frequency down-spread at maximum 60 khz modulation rate regardless of input frequency. note: pci ac timing the soc meets the timing requirements of pci specification revision 2.2 . see section 7, ?clock configuration modes ,? and ?note: tval (output hold)? to determine if a specific clock configuration is compliant. sys clk pio/idma/timer[tgate assertion] input signals idma output signals sp22 sp23 sp42/sp43 timer(sp42/43)/ pio(sp42a/sp43a) sp42a/sp43a output signals sp42/sp43 timer input signal [tgate deassertion] sp22 sp23 note: tgate is asserted on the rising edge of the clock; it is deasserted on the falling edge. (see note) (see note)
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 23 ac electrical characteristics note: conditions the following conditions must be me t in order to operate the mpc8272 family devices with 133 mhz bus: single powerquicc ii bus mode must be used (no external master, bcr[ebm] = 0); data bus must be in pipeline mode (brx[dr] = 1); internal arbiter and memory controller must be used. for expected load of above 40 pf, it is recommended that data and address buses be configured to low (25 ) impedance (siumcr[hlbe0] = 1, siumcr[hlbe1] = 1). this table lists siu output characteristics. table 12. ac characteristics for siu inputs 1 1 input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. spec number characteristic value (ns) setup hold setup hold 66 mhz 83 mhz 100 mhz 133 mhz 66 mhz 83 mhz 100 mhz 133 mhz sp11 sp10 aack /ta /ts /dbg /bg /br /artry /tea 6 5 3.5 n/a 0.5 0.5 0.5 n/a sp12 sp10 data bus in normal mode 5 4 3.5 n/a 0.5 0.5 0.5 n/a sp13 sp10 data bus in pipeline mode (without ecc and pa r i t y ) n/a 4 2.5 1.5 n/a 0.5 0.5 0.5 sp15 sp10 all other pins 5 4 3.5 n/a 0.5 0.5 0.5 n/a table 13. ac characteristics for siu outputs 1 1 output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. spec number characteristic value (ns) max min maximum delay minimum delay 66 mhz 83 mhz 100 mhz 133 mhz 66 mhz 83 mhz 100 mhz 133 mhz sp31 sp30 psdval /tea /ta 7 6 5.5 n/a 1 1 1 n/a sp32 sp30 add/add_atr./baddr/ci/gbl/wt 8 6.5 5.5 4.5 2 2 value is for add only; other sp32/sp30 signals are not applicable. 1111 2 sp33 sp30 data bus 3 3 to achieve 1 ns of hold time at 66.67/83.33/100 mhz, a minimum loading of 20 pf is required. 6.5 6.5 5.5 4.5 0.8 0.8 0.8 1 sp34 sp30 memory controller signals/ale 6 5.5 5.5 4.5 1 1 1 1 sp35 sp30 all other signals 6 5.5 5.5 n/a 1 1 1 n/a
mpc8272 powerquicc ii family hardware specifications, rev. 3 24 freescale semiconductor ac electrical characteristics note activating data pi pelining (setting br x [dr] in the memory controller) improves the ac timing. this figure shows the interaction of several bus signals. figure 9. bus signals clkin aack /ta /ts / data bus normal mode all other input signals psdval /tea /ta output signals add/add_atr/baddr/ci/ data bus output signals all other output signals sp11 sp12 sp15 sp10 sp10 sp10 sp30 sp30 sp30 sp30 sp32 sp33 sp35 dbg /bg /br input signals gbl/wt output signals sp31 input signal artry /tea input signals sp11a sp10 (except ap) sp10 sp13 data bus pipeline mode input signal
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 25 ac electrical characteristics this figure shows signal behavior in memc mode. figure 10. memc mode diagram note generally, all soc bus and system output signals are driven from the rising edge of the input clock (clkin). memory controller signals, however, trigger on four points within a clkin cycle. each cycle is divided by four internal ticks: t1, t2, t3, and t4. t1 always occurs at the rising edge, and t3 at the falling edge, of clkin. however, the spacing of t2 and t4 depends on the pll clock ratio selected, as shown in table 14 . this table is a representation of the information in table 14 . figure 11. internal tick spacing for memory controller signals table 14. tick spacing for memory controller signals pll clock ratio tick spacing (t1 occurs at the rising edge of clkin) t2 t3 t4 1:2, 1:3, 1:4, 1:5, 1:6 1/4 clkin 1/2 clkin 3/4 clkin 1:2.5 3/10 clkin 1/2 clkin 8/10 clkin 1:3.5 4/14 clkin 1/2 clkin 11/14 clkin clkin v_clk memory controller signals sp34/sp30 clkin t1 t2 t3 t4 clkin t1 t2 t3 t4 for 1:2.5 for 1:3.5 clkin t1 t2 t3 t4 for 1:2, 1:3, 1:4, 1:5, 1:6
mpc8272 powerquicc ii family hardware specifications, rev. 3 26 freescale semiconductor ac electrical characteristics note the upm machine outputs change on the internal tick determined by the memory controller programming; the ac specifications are relative to the internal tick. note that sdram and gpcm machine outputs change on clkin?s rising edge. 6.3 jtag timings this table lists the jtag timings. table 15. jtag timings 1 parameter symbol 2 min max unit notes jtag external clock frequency of operation f jtg 033.3mhz? jtag external clock cycle time t jtg 30 ? ns ? jtag external clock pulse width measured at 1.4v t jtkhkl 15 ? ns ? jtag external clock rise and fall times t jtgr and t jtgf 05ns 6 trst assert time t trst 25 ? ns 3 , 6 input setup times boundary-scan data tms, tdi t jtdvkh t jtivkh 4 4 ? ? ns ns 4 , 7 4 , 7 input hold times boundary-scan data tms, tdi t jtdxkh t jtixkh 10 10 ? ? ns ns 4 , 7 4 , 7 output valid times boundary-scan data tdo t jtkldv t jtklov ? ? 10 10 ns ns 5 , 7 5 . 7 output hold times boundary-scan data tdo t jtkldx t jtklox 1 1 ? ? ns ns 5 , 7 5 , 7 jtag external clock to output high impedance boundary-scan data tdo t jtkldz t jtkloz 1 1 10 10 ns ns 5 , 6 5 , 6 1 all outputs are measured from the midpoint voltage of the falling/rising edge of t tclk to the midpoint of the signal in question. the output timings are measured at the pins. all output timings assume a purely resistive 50- load. time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2 the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t( (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t jtdvkh symbolizes jtag device timing (jt) with respect to the time data input signals (d) reaching the valid state (v) relative to the t jtg clock reference (k) going to the high (h) state or setup time. also, t jtdxkh symbolizes jtag timing (jt) with respect to the time data input signals (d) went invalid (x) relative to the t jtg clock reference (k) going to the high (h) state. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 3 trst is an asynchronous level sensitive signal. the setup time is for test purposes only. 4 non-jtag signal input timing with respect to t tclk . 5 non-jtag signal output timing with respect to t tclk . 6 guaranteed by design. 7 guaranteed by design and device characterization.
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 27 clock configuration modes 7 clock configuration modes as shown in this table, the clocking mode is set according to two sources: ? pci_cfg[0]? an input signal. also defined as ?pci_host_en .? see chapter 6, ?external signals,? and chapter 9, ?pci bri dge,? in the soc reference manual. ? pci_modck?bit 27 in the hard reset configuration word. see chapter 5, ?reset,? in the soc reference manual. within each mode, the configuration of bus, core, pci, and cpm frequencies is determined by seven bits during the power-on reset?three hardware configuration pins (modck[1?3]) and four bits from hardware configuration word[28?31] (modck_h). both the plls and the dividers are set according to the selected clock operation mode as described in the following sections. note clock configurations ch ange only after poreset is asserted. note: tval (output hold) the minimum tval = 2 ns when pci_modck = 1, and the minimum tval = 1 ns when pci_modck = 0. therefore, designers should use clock configurations that fit this condition to achieve pci-compliant ac timing. 7.1 pci host mode these tables show configurations for pci host mode . the frequency values listed are for the purpose of illustration only. users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user?s device. note that in pci host mode the input clock is the bus clock. table 16. soc clocking modes pins clocking mode pci clock frequency range (mhz) reference pci_cfg[0] 1 1 pci_host_en pci_modck 2 2 determines pci clock frequency range. 0 0 pci host 50?66 ta b l e 1 7 0 1 25?50 ta b l e 1 8 1 0 pci agent 50?66 ta b l e 1 9 1 1 25?50 ta b l e 2 0
mpc8272 powerquicc ii family hardware specifications, rev. 3 28 freescale semiconductor clock configuration modes table 17. clock configurations for pci host mode (pci_modck=0) 1,2 mode 3 bus clock (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) pci division factor 6 pci clock (mhz) modck_h- modck[1-3] low high low high low high low high default modes (modck_h=0000) 0000_000 60.0 66.7 2 120.0 133.3 2.5 150.0 166.7 2 60.0 66.7 0000_001 50.0 66.7 2 100.0 133.3 3 150.0 200.0 2 50.0 66.7 0000_010 60.0 80.0 2.5 150.0 200.0 3 180.0 240.0 3 50.0 66.7 0000_011 60.0 80.0 2.5 150.0 200.0 3.5 210.0 280.0 3 50.0 66.7 0000_100 60.0 80.0 2.5 150.0 200.0 4 240.0 320.0 3 50.0 66.7 0000_101 50.0 66.7 3 150.0 200.0 3 150.0 200.0 3 50.0 66.7 0000_110 50.0 66.7 3.5 150.0 200.0 3.5 175.0 233.3 3 50.0 66.7 0000_111 50.0 66.7 3 150.0 200.0 4 200.0 266.6 3 50.0 66.7 full configuration modes 0001_000 50.0 66.7 3 150.0 200.0 5 250.0 333.3 3 50.0 66.7 0001_001 50.0 66.7 3 150.0 200.0 6 300.0 400.0 3 50.0 66.7 0001_010 50.0 66.7 3 150.0 200.0 7 350.0 466.6 3 50.0 66.7 0001_011 50.0 66.7 3 150.0 200.0 8 400.0 533.3 3 50.0 66.7 0010_000 50.0 66.7 4 200.0 266.6 5 250.0 333.3 4 50.0 66.7 0010_001 50.0 66.7 4 200.0 266.6 6 300.0 400.0 4 50.0 66.7 0010_010 50.0 66.7 4 200.0 266.6 7 350.0 466.6 4 50.0 66.7 0010_011 50.0 66.7 4 200.0 266.6 8 400.0 533.3 4 50.0 66.7 0010_100 75.0 100.0 4 300.0 400.0 5 375.0 500.0 6 50.0 66.7 0010_101 75.0 100.0 4 300.0 400.0 5.5 412.5 549.9 6 50.0 66.7 0010_110 75.0 100.0 4 300.0 400.0 6 450.0 599.9 6 50.0 66.7 0011_000 50.0 66.7 5 250.0 333.3 5 250.0 333.3 5 50.0 66.7 0011_001 50.0 66.7 5 250.0 333.3 6 300.0 400.0 5 50.0 66.7 0011_010 50.0 66.7 5 250.0 333.3 7 350.0 466.6 5 50.0 66.7 0011_011 50.0 66.7 5 250.0 333.3 8 400.0 533.3 5 50.0 66.7 0100_000 reserved
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 29 clock configuration modes 0100_001 50.0 66.7 6 300.0 400.0 6 300.0 400.0 6 50.0 66.7 0100_010 50.0 66.7 6 300.0 400.0 7 350.0 466.6 6 50.0 66.7 0100_011 50.0 66.7 6 300.0 400.0 8 400.0 533.3 6 50.0 66.7 0101_000 60.0 66.7 2 120.0 133.3 2.5 150.0 166.7 2 60.0 66.7 0101_001 50.0 66.7 2 100.0 133.3 3 150.0 200.0 2 50.0 66.7 0101_010 50.0 66.7 2 100.0 133.3 3.5 175.0 233.3 2 50.0 66.7 0101_011 50.0 66.7 2 100.0 133.3 4 200.0 266.6 2 50.0 66.7 0101_100 50.0 66.7 2 100.0 133.3 4.5 225.0 300.0 2 50.0 66.7 0101_101 83.3 111.1 3 250.0 333.3 3.5 291.7 388.9 5 50.0 66.7 0101_110 83.3 111.1 3 250.0 333.3 4 333.3 444.4 5 50.0 66.7 0101_111 83.3 111.1 3 250.0 333.3 4.5 375.0 500.0 5 50.0 66.7 0110_000 60.0 80.0 2.5 150.0 200.0 2.5 150.0 200.0 3 50.0 66.7 0110_001 60.0 80.0 2.5 150.0 200.0 3 180.0 240.0 3 50.0 66.7 0110_010 60.0 80.0 2.5 150.0 200.0 3.5 210.0 280.0 3 50.0 66.7 0110_011 60.0 80.0 2.5 150.0 200.0 4 240.0 320.0 3 50.0 66.7 0110_100 60.0 80.0 2.5 150.0 200.0 4.5 270.0 360.0 3 50.0 66.7 0110_101 60.0 80.0 2.5 150.0 200.0 5 300.0 400.0 3 50.0 66.7 0110_110 60.0 80.0 2.5 150.0 200.0 6 360.0 480.0 3 50.0 66.7 0111_000 reserved 0111_001 50.0 66.7 3 150.0 200.0 3 150.0 200.0 3 50.0 66.7 0111_010 50.0 66.7 3 150.0 200.0 3.5 175.0 233.3 3 50.0 66.7 0111_011 50.0 66.7 3 150.0 200.0 4 200.0 266.6 3 50.0 66.7 0111_100 50.0 66.7 3 150.0 200.0 4.5 225.0 300.0 3 50.0 66.7 1000_000 reserved 1000_001 66.7 88.9 3 200.0 266.6 3 200.0 266.6 4 50.0 66.7 table 17. clock configurations for pci host mode (pci_modck=0) 1,2 (continued) mode 3 bus clock (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) pci division factor 6 pci clock (mhz) modck_h- modck[1-3] low high low high low high low high
mpc8272 powerquicc ii family hardware specifications, rev. 3 30 freescale semiconductor clock configuration modes 1000_010 66.7 88.9 3 200.0 266.6 3.5 233.3 311.1 4 50.0 66.7 1000_011 66.7 88.9 3 200.0 266.6 4 266.7 355.5 4 50.0 66.7 1000_100 66.7 88.9 3 200.0 266.6 4.5 300.0 400.0 4 50.0 66.7 1000_101 66.7 88.9 3 200.0 266.6 6 400.0 533.3 4 50.0 66.7 1000_110 66.7 88.9 3 200.0 266.6 6.5 433.3 577.7 4 50.0 66.7 1001_000 reserved 1001_001 reserved 1001_010 57.1 76.2 3.5 200.0 266.6 3.5 200.0 266.6 4 50.0 66.7 1001_011 57.1 76.2 3.5 200.0 266.6 4 228.6 304.7 4 50.0 66.7 1001_100 57.1 76.2 3.5 200.0 266.6 4.5 257.1 342.8 4 50.0 66.7 1001_101 85.7 114.3 3.5 300.0 400.0 5 428.6 571.4 6 50.0 66.7 1001_110 85.7 114.3 3.5 300.0 400.0 5.5 471.4 628.5 6 50.0 66.7 1001_111 85.7 114.3 3.5 300.0 400.0 6 514.3 685.6 6 50.0 66.7 1010_000 75.0 100.0 2 150.0 200.0 2 150.0 200.0 3 50.0 66.7 1010_001 75.0 100.0 2 150.0 200.0 2.5 187.5 250.0 3 50.0 66.7 1010_010 75.0 100.0 2 150.0 200.0 3 225.0 300.0 3 50.0 66.7 1010_011 75.0 100.0 2 150.0 200.0 3.5 262.5 350.0 3 50.0 66.7 1010_100 75.0 100.0 2 150.0 200.0 4 300.0 400.0 3 50.0 66.7 1010_101 100.0 133.3 2 200.0 266.6 2.5 250.0 333.3 4 50.0 66.7 1010_110 100.0 133.3 2 200.0 266.6 3 300.0 400.0 4 50.0 66.7 1010_111 100.0 133.3 2 200.0 266.6 3.5 350.0 466.6 4 50.0 66.7 1011_000 reserved 1011_001 80.0 106.7 2.5 200.0 266.6 2.5 200.0 266.6 4 50.0 66.7 1011_010 80.0 106.7 2.5 200.0 266.6 3 240.0 320.0 4 50.0 66.7 1011_011 80.0 106.7 2.5 200.0 266.6 3.5 280.0 373.3 4 50.0 66.7 table 17. clock configurations for pci host mode (pci_modck=0) 1,2 (continued) mode 3 bus clock (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) pci division factor 6 pci clock (mhz) modck_h- modck[1-3] low high low high low high low high
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 31 clock configuration modes 1011_100 80.0 106.7 2.5 200.0 266.6 4 320.0 426.6 4 50.0 66.7 1011_101 80.0 106.7 2.5 200.0 266.6 4.5 360.0 480.0 4 50.0 66.7 1101_000 100.0 133.3 2.5 250.0 333.3 3 300.0 400.0 5 50.0 66.7 1101_001 100.0 133.3 2.5 250.0 333.3 3.5 350.0 466.6 5 50.0 66.7 1101_010 100.0 133.3 2.5 250.0 333.3 4 400.0 533.3 5 50.0 66.7 1101_011 100.0 133.3 2.5 250.0 333.3 4.5 450.0 599.9 5 50.0 66.7 1101_100 100.0 133.3 2.5 250.0 333.3 5 500.0 666.6 5 50.0 66.7 1101_101 125.0 166.7 2 250.0 333.3 3 375.0 500.0 5 50.0 66.7 1101_110 125.0 166.7 2 250.0 333.3 4 500.0 666.6 5 50.0 66.7 1110_000 100.0 133.3 3 300.0 400.0 3.5 350.0 466.6 6 50.0 66.7 1110_001 100.0 133.3 3 300.0 400.0 4 400.0 533.3 6 50.0 66.7 1110_010 100.0 133.3 3 300.0 400.0 4.5 450.0 599.9 6 50.0 66.7 1110_011 100.0 133.3 3 300.0 400.0 5 500.0 666.6 6 50.0 66.7 1110_100 100.0 133.3 3 300.0 400.0 5.5 550.0 733.3 6 50.0 66.7 1100_000 reserved 1100_001 reserved 1100_010 reserved 1 the ?low? values are the minimum allowable frequencies for a given clock mode. the minimum bus frequency in a table entry guarantees only the required minimum cpu operating frequency. the ?high? values are for the purpose of illustration only. users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user?s device. the minimum cpu frequency is 150 mhz for commercial temperature devices and 175 mhz for extended temperature devices. the minimum cpm frequency is 120 mhz. 2 pci_modck determines the pci clock frequency range. see ta b l e 1 8 for lower range configurations. 3 modck_h = hard reset configuration word [28?31] (see section 5.4 in the soc reference manual). modck[1-3] = three hardware configuration pins. 4 cpm multiplication factor = cpm clock/bus clock 5 cpu multiplication factor = core pll multiplication factor 6 cpm_clk/pci_clk ratio. when pci_modck = 0, the ratio of cpm_clk/pci_clk should be calculated from sccr[pcidf] as follows: cpm_clk/pci_clk = (pcidf + 1) / 2. table 17. clock configurations for pci host mode (pci_modck=0) 1,2 (continued) mode 3 bus clock (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) pci division factor 6 pci clock (mhz) modck_h- modck[1-3] low high low high low high low high
mpc8272 powerquicc ii family hardware specifications, rev. 3 32 freescale semiconductor clock configuration modes table 18. clock configurations for pci host mode (pci_modck=1) 1,2 mode 3 bus clock (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) pci division factor 6 pci clock (mhz) modck_h- modck[1-3] low high low high low high low high default modes (modck_h=0000) 0000_000 60.0 100.0 2 120.0 200.0 2.5 150.0 250.0 4 30.0 50.0 0000_001 50.0 100.0 2 100.0 200.0 3 150.0 300.0 4 25.0 50.0 0000_010 60.0 120.0 2.5 150.0 300.0 3 180.0 360.0 6 25.0 50.0 0000_011 60.0 120.0 2.5 150.0 300.0 3.5 210.0 420.0 6 25.0 50.0 0000_100 60.0 120.0 2.5 150.0 300.0 4 240.0 480.0 6 25.0 50.0 0000_101 50.0 100.0 3 150.0 300.0 3 150.0 300.0 6 25.0 50.0 0000_110 50.0 100.0 3 150.0 300.0 3.5 175.0 350.0 6 25.0 50.0 0000_111 50.0 100.0 3 150.0 300.0 4 200.0 400.0 6 25.0 50.0 full configuration modes 0001_000 50.0 100.0 3 150.0 300.0 5 250.0 500.0 6 25.0 50.0 0001_001 50.0 100.0 3 150.0 300.0 6 300.0 600.0 6 25.0 50.0 0001_010 50.0 100.0 3 150.0 300.0 7 350.0 700.0 6 25.0 50.0 0001_011 50.0 100.0 3 150.0 300.0 8 400.0 800.0 6 25.0 50.0 0010_000 50.0 100.0 4 200.0 400.0 5 250.0 500.0 8 25.0 50.0 0010_001 50.0 100.0 4 200.0 400.0 6 300.0 600.0 8 25.0 50.0 0010_010 50.0 100.0 4 200.0 400.0 7 350.0 700.0 8 25.0 50.0 0010_011 50.0 100.0 4 200.0 400.0 8 400.0 800.0 8 25.0 50.0 0010_100 37.5 75.0 4 150.0 300.0 5 187.5 375.0 6 25.0 50.0 0010_101 37.5 75.0 4 150.0 300.0 5.5 206.3 412.5 6 25.0 50.0 0010_110 37.5 75.0 4 150.0 300.0 6 225.0 450.0 6 25.0 50.0 0011_000 30.0 50.0 5 150.0 250.0 5 150.0 250.0 5 30.0 50.0 0011_001 25.0 50.0 5 125.0 250.0 6 150.0 300.0 5 25.0 50.0 0011_010 25.0 50.0 5 125.0 250.0 7 175.0 350.0 5 25.0 50.0 0011_011 25.0 50.0 5 125.0 250.0 8 200.0 400.0 5 25.0 50.0 0100_000 reserved
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 33 clock configuration modes 0100_001 25.0 50.0 6 150.0 300.0 6 150.0 300.0 6 25.0 50.0 0100_010 25.0 50.0 6 150.0 300.0 7 175.0 350.0 6 25.0 50.0 0100_011 25.0 50.0 6 150.0 300.0 8 200.0 400.0 6 25.0 50.0 0101_000 60.0 100.0 2 120.0 200.0 2.5 150.0 250.0 4 30.0 50.0 0101_001 50.0 100.0 2 100.0 200.0 3 150.0 300.0 4 25.0 50.0 0101_010 50.0 100.0 2 100.0 200.0 3.5 175.0 350.0 4 25.0 50.0 0101_011 50.0 100.0 2 100.0 200.0 4 200.0 400.0 4 25.0 50.0 0101_100 50.0 100.0 2 100.0 200.0 4.5 225.0 450.0 4 25.0 50.0 0101_101 42.9 83.3 3 128.6 250.0 3.5 150.0 291.7 5 25.7 50.0 0101_110 41.7 83.3 3 125.0 250.0 4 166.7 333.3 5 25.0 50.0 0101_111 41.7 83.3 3 125.0 250.0 4.5 187.5 375.0 5 25.0 50.0 0110_000 60.0 120.0 2.5 150.0 300.0 2.5 150.0 300.0 6 25.0 50.0 0110_001 60.0 120.0 2.5 150.0 300.0 3 180.0 360.0 6 25.0 50.0 0110_010 60.0 120.0 2.5 150.0 300.0 3.5 210.0 420.0 6 25.0 50.0 0110_011 60.0 120.0 2.5 150.0 300.0 4 240.0 480.0 6 25.0 50.0 0110_100 60.0 120.0 2.5 150.0 300.0 4.5 270.0 540.0 6 25.0 50.0 0110_101 60.0 120.0 2.5 150.0 300.0 5 300.0 600.0 6 25.0 50.0 0110_110 60.0 120.0 2.5 150.0 300.0 6 360.0 720.0 6 25.0 50.0 0111_000 reserved 0111_001 50.0 100.0 3 150.0 300.0 3 150.0 300.0 6 25.0 50.0 0111_010 50.0 100.0 3 150.0 300.0 3.5 175.0 350.0 6 25.0 50.0 0111_011 50.0 100.0 3 150.0 300.0 4 200.0 400.0 6 25.0 50.0 0111_100 50.0 100.0 3 150.0 300.0 4.5 225.0 450.0 6 25.0 50.0 1000_000 reserved 1000_001 66.7 133.3 3 200.0 400.0 3 200.0 400.0 8 25.0 50.0 table 18. clock configurations for pci host mode (pci_modck=1) 1,2 (continued) mode 3 bus clock (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) pci division factor 6 pci clock (mhz) modck_h- modck[1-3] low high low high low high low high
mpc8272 powerquicc ii family hardware specifications, rev. 3 34 freescale semiconductor clock configuration modes 1000_010 66.7 133.3 3 200.0 400.0 3.5 233.3 466.7 8 25.0 50.0 1000_011 66.7 133.3 3 200.0 400.0 4 266.7 533.3 8 25.0 50.0 1000_100 66.7 133.3 3 200.0 400.0 4.5 300.0 600.0 8 25.0 50.0 1000_101 66.7 133.3 3 200.0 400.0 6 400.0 800.0 8 25.0 50.0 1000_110 66.7 133.3 3 200.0 400.0 6.5 433.3 866.7 8 25.0 50.0 1001_000 reserved 1001_001 reserved 1001_010 57.1 114.3 3.5 200.0 400.0 3.5 200.0 400.0 8 25.0 50.0 1001_011 57.1 114.3 3.5 200.0 400.0 4 228.6 457.1 8 25.0 50.0 1001_100 57.1 114.3 3.5 200.0 400.0 4.5 257.1 514.3 8 25.0 50.0 1001_101 42.9 85.7 3.5 150.0 300.0 5 214.3 428.6 6 25.0 50.0 1001_110 42.9 85.7 3.5 150.0 300.0 5.5 235.7 471.4 6 25.0 50.0 1001_111 42.9 85.7 3.5 150.0 300.0 6 257.1 514.3 6 25.0 50.0 1010_000 75.0 150.0 2 150.0 300.0 2 150.0 300.0 6 25.0 50.0 1010_001 75.0 150.0 2 150.0 300.0 2.5 187.5 375.0 6 25.0 50.0 1010_010 75.0 150.0 2 150.0 300.0 3 225.0 450.0 6 25.0 50.0 1010_011 75.0 150.0 2 150.0 300.0 3.5 262.5 525.0 6 25.0 50.0 1010_100 75.0 150.0 2 150.0 300.0 4 300.0 600.0 6 25.0 50.0 1010_101 100.0 200.0 2 200.0 400.0 2.5 250.0 500.0 8 25.0 50.0 1010_110 100.0 200.0 2 200.0 400.0 3 300.0 600.0 8 25.0 50.0 1010_111 100.0 200.0 2 200.0 400.0 3.5 350.0 700.0 8 25.0 50.0 1011_000 reserved 1011_001 80.0 160.0 2.5 200.0 400.0 2.5 200.0 400.0 8 25.0 50.0 1011_010 80.0 160.0 2.5 200.0 400.0 3 240.0 480.0 8 25.0 50.0 1011_011 80.0 160.0 2.5 200.0 400.0 3.5 280.0 560.0 8 25.0 50.0 1011_100 80.0 160.0 2.5 200.0 400.0 4 320.0 640.0 8 25.0 50.0 table 18. clock configurations for pci host mode (pci_modck=1) 1,2 (continued) mode 3 bus clock (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) pci division factor 6 pci clock (mhz) modck_h- modck[1-3] low high low high low high low high
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 35 clock configuration modes 1011_101 80.0 160.0 2.5 200.0 400.0 4.5 360.0 720.0 8 25.0 50.0 1101_000 50.0 100.0 2.5 125.0 250.0 3 150.0 300.0 5 25.0 50.0 1101_001 50.0 100.0 2.5 125.0 250.0 3.5 175.0 350.0 5 25.0 50.0 1101_010 50.0 100.0 2.5 125.0 250.0 4 200.0 400.0 5 25.0 50.0 1101_011 50.0 100.0 2.5 125.0 250.0 4.5 225.0 450.0 5 25.0 50.0 1101_100 50.0 100.0 2.5 125.0 250.0 5 250.0 500.0 5 25.0 50.0 1101_101 62.5 125.0 2 125.0 250.0 3 187.5 375.0 5 25.0 50.0 1101_110 62.5 125.0 2 125.0 250.0 4 250.0 500.0 5 25.0 50.0 1110_000 50.0 100.0 3 150.0 300.0 3.5 175.0 350.0 6 25.0 50.0 1110_001 50.0 100.0 3 150.0 300.0 4 200.0 400.0 6 25.0 50.0 1110_010 50.0 100.0 3 150.0 300.0 4.5 225.0 450.0 6 25.0 50.0 1110_011 50.0 100.0 3 150.0 300.0 5 250.0 500.0 6 25.0 50.0 1110_100 50.0 100.0 3 150.0 300.0 5.5 275.0 550.0 6 25.0 50.0 1100_000 reserved 1100_001 reserved 1100_010 reserved 1 the ?low? values are the minimum allowable frequencies for a given clock mode. the minimum bus frequency in a table entry guarantees only the required minimum cpu operating frequency. the ?high? values are for the purpose of illustration only. users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user?s device. the minimum cpu frequency is 150 mhz for commercial temperature devices and 175 mhz for extended temperature devices. the minimum cpm frequency is 120 mhz. 2 pci_modck determines the pci clock frequency range. see table 17 for higher range configurations. 3 modck_h = hard reset configuration word [28?31] (see section 5.4 in the soc reference manual). modck[1-3] = three hardware configuration pins. 4 cpm multiplication factor = cpm clock/bus clock 5 cpu multiplication factor = core pll multiplication factor table 18. clock configurations for pci host mode (pci_modck=1) 1,2 (continued) mode 3 bus clock (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) pci division factor 6 pci clock (mhz) modck_h- modck[1-3] low high low high low high low high
mpc8272 powerquicc ii family hardware specifications, rev. 3 36 freescale semiconductor clock configuration modes 7.2 pci agent mode these tables show configurations for pci agent mode . the frequency values listed are for the purpose of illustration only. users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user?s device. note that in pci agent mode the input clock is pci clock. 6 cpm_clk/pci_clk ratio. when pci_modck = 1, the ratio of cpm_clk/pci_clk should be calculated from pcidf as follows: pcidf = 3 > cpm_clk/pci_clk = 4 pcidf = 5 > cpm_clk/pci_clk = 6 pcidf = 7 > cpm_clk/pci_clk = 8 pcidf = 9 > cpm_clk/pci_clk = 5 pcidf = b > cpm_clk/pci_clk = 6 table 19. clock configurations for pci agent mode (pci_modck=0) 1,2 mode 3 pci clock (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) bus division factor bus clock (mhz) modck_h- modck[1-3] low high low high low high low high default modes (modck_h=0000) 0000_000 60.0 66.7 2 120.0 133.3 2.5 150.0 166.7 2 60.0 66.7 0000_001 50.0 66.7 2 100.0 133.3 3 150.0 200.0 2 50.0 66.7 0000_010 50.0 66.7 3 150.0 200.0 3 150.0 200.0 3 50.0 66.7 0000_011 50.0 66.7 3 150.0 200.0 4 200.0 266.6 3 50.0 66.7 0000_100 50.0 66.7 3 150.0 200.0 3 180.0 240.0 2.5 60.0 80.0 0000_101 50.0 66.7 3 150.0 200.0 3.5 210.0 280.0 2.5 60.0 80.0 0000_110 50.0 66.7 4 200.0 266.6 3.5 233.3 311.1 3 66.7 88.9 0000_111 50.0 66.7 4 200.0 266.6 3 240.0 320.0 2.5 80.0 106.7 full configuration modes 0001_001 60.0 66.7 2 120.0 133.3 5 150.0 166.7 4 30.0 33.3 0001_010 50.0 66.7 2 100.0 133.3 6 150.0 200.0 4 25.0 33.3 0001_011 50.0 66.7 2 100.0 133.3 7 175.0 233.3 4 25.0 33.3 0001_100 50.0 66.7 2 100.0 133.3 8 200.0 266.6 4 25.0 33.3 0010_001 50.0 66.7 3 150.0 200.0 3 180.0 240.0 2.5 60.0 80.0 0010_010 50.0 66.7 3 150.0 200.0 3.5 210.0 280.0 2.5 60.0 80.0 0010_011 50.0 66.7 3 150.0 200.0 4 240.0 320.0 2.5 60.0 80.0 0010_100 50.0 66.7 3 150.0 200.0 4.5 270.0 360.0 2.5 60.0 80.0
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 37 clock configuration modes 0011_000 reserved 0011_001 reserved 0011_010 reserved 0011_011 reserved 0011_100 reserved 0100_000 reserved 0100_001 50.0 66.7 3 150.0 200.0 3 150.0 200.0 3 50.0 66.7 0100_010 50.0 66.7 3 150.0 200.0 3.5 175.0 200.0 3 50.0 66.7 0100_011 50.0 66.7 3 150.0 200.0 4 200.0 266.6 3 50.0 66.7 0100_100 50.0 66.7 3 150.0 200.0 4.5 225.0 300.0 3 50.0 66.7 0101_000 50.0 66.7 5 250.0 333.3 2.5 250.0 333.3 2.5 100.0 133.3 0101_001 50.0 66.7 5 250.0 333.3 3 300.0 400.0 2.5 100.0 133.3 0101_010 50.0 66.7 5 250.0 333.3 3.5 350.0 466.6 2.5 100.0 133.3 0101_011 50.0 66.7 5 250.0 333.3 4 400.0 533.3 2.5 100.0 133.3 0101_100 50.0 66.7 5 250.0 333.3 4.5 450.0 599.9 2.5 100.0 133.3 0101_101 50.0 66.7 5 250.0 333.3 5 500.0 666.6 2.5 100.0 133.3 0101_110 50.0 66.7 5 250.0 333.3 5.5 550.0 733.3 2.5 100.0 133.3 0110_000 reserved 0110_001 50.0 66.7 4 200.0 266.6 3 200.0 266.6 3 66.7 88.9 0110_010 50.0 66.7 4 200.0 266.6 3.5 233.3 311.1 3 66.7 88.9 0110_011 50.0 66.7 4 200.0 266.6 4 266.7 355.5 3 66.7 88.9 0110_100 50.0 66.7 4 200.0 266.6 4.5 300.0 400.0 3 66.7 88.9 0111_000 50.0 66.7 3 150.0 200.0 2 150.0 200.0 2 75.0 100.0 0111_001 50.0 66.7 3 150.0 200.0 2.5 187.5 250.0 2 75.0 100.0 0111_010 50.0 66.7 3 150.0 200.0 3 225.0 300.0 2 75.0 100.0 0111_011 50.0 66.7 3 150.0 200.0 3.5 262.5 350.0 2 75.0 100.0 table 19. clock configurations for pci agent mode (pci_modck=0) 1,2 (continued) mode 3 pci clock (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) bus division factor bus clock (mhz) modck_h- modck[1-3] low high low high low high low high
mpc8272 powerquicc ii family hardware specifications, rev. 3 38 freescale semiconductor clock configuration modes 1000_000 reserved 1000_001 50.0 66.7 3 150.0 200.0 2.5 150.0 166.7 2.5 60.0 80.0 1000_010 50.0 66.7 3 150.0 200.0 3 180.0 240.0 2.5 60.0 80.0 1000_011 50.0 66.7 3 150.0 200.0 3.5 210.0 280.0 2.5 60.0 80.0 1000_100 50.0 66.7 3 150.0 200.0 4 240.0 320.0 2.5 60.0 80.0 1000_101 50.0 66.7 3 150.0 200.0 4.5 270.0 360.0 2.5 60.0 80.0 1001_000 reserved 1001_001 reserved 1001_010 reserved 1001_011 50.0 66.7 4 200.0 266.6 4 200.0 266.6 4 50.0 66.7 1001_100 50.0 66.7 4 200.0 266.6 4.5 225.0 300.0 4 50.0 66.7 1010_000 reserved 1010_001 50.0 66.7 4 200.0 266.6 3 200.0 266.6 3 66.7 88.9 1010_010 50.0 66.7 4 200.0 266.6 3.5 233.3 311.1 3 66.7 88.9 1010_011 50.0 66.7 4 200.0 266.6 4 266.7 355.5 3 66.7 88.9 1010_100 50.0 66.7 4 200.0 266.6 4.5 300.0 400.0 3 66.7 88.9 1011_000 reserved 1011_001 50.0 66.7 4 200.0 266.6 2.5 200.0 266.6 2.5 80.0 106.7 1011_010 50.0 66.7 4 200.0 266.6 3 240.0 320.0 2.5 80.0 106.7 1011_011 50.0 66.7 4 200.0 266.6 3.5 280.0 373.3 2.5 80.0 106.7 1011_100 50.0 66.7 4 200.0 266.6 4 320.0 426.6 2.5 80.0 106.7 1011_101 50.0 66.7 4 200.0 266.6 2.5 250.0 333.3 2 100.0 133.3 1011_110 50.0 66.7 4 200.0 266.6 3 300.0 400.0 2 100.0 133.3 1011_111 50.0 66.7 4 200.0 266.6 3.5 350.0 466.6 2 100.0 133.3 table 19. clock configurations for pci agent mode (pci_modck=0) 1,2 (continued) mode 3 pci clock (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) bus division factor bus clock (mhz) modck_h- modck[1-3] low high low high low high low high
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 39 clock configuration modes 1100_101 50.0 66.7 6 300.0 400.0 4 400.0 533.3 3 100.0 133.3 1100_110 50.0 66.7 6 300.0 400.0 4.5 450.0 599.9 3 100.0 133.3 1100_111 50.0 66.7 6 300.0 400.0 5 500.0 666.6 3 100.0 133.3 1101_000 50.0 66.7 6 300.0 400.0 5.5 550.0 733.3 3 100.0 133.3 1101_001 50.0 66.7 6 300.0 400.0 3.5 420.0 559.9 2.5 120.0 160.0 1101_010 50.0 66.7 6 300.0 400.0 4 480.0 639.9 2.5 120.0 160.0 1101_011 50.0 66.7 6 300.0 400.0 4.5 540.0 719.9 2.5 120.0 160.0 1101_100 50.0 66.7 6 300.0 400.0 5 600.0 799.9 2.5 120.0 160.0 1110_000 50.0 66.7 5 250.0 333.3 2.5 312.5 416.6 2 125.0 166.7 1110_001 50.0 66.7 5 250.0 333.3 3 375.0 500.0 2 125.0 166.7 1110_010 50.0 66.7 5 250.0 333.3 3.5 437.5 583.3 2 125.0 166.7 1110_011 50.0 66.7 5 250.0 333.3 4 500.0 666.6 2 125.0 166.7 1110_100 50.0 66.7 5 250.0 333.3 4 333.3 444.4 3 83.3 111.1 1110_101 50.0 66.7 5 250.0 333.3 4.5 375.0 500.0 3 83.3 111.1 1110_110 50.0 66.7 5 250.0 333.3 5 416.7 555.5 3 83.3 111.1 1110_111 50.0 66.7 5 250.0 333.3 5.5 458.3 611.1 3 83.3 111.1 1100_000 reserved 1100_001 reserved 1100_010 reserved 1 the ?low? values are the minimum allowable frequencies for a given clock mode. the minimum bus frequency in a table entry guarantees only the required minimum cpu operating frequency. the ?high? values are for the purpose of illustration only. users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user?s device. the minimum cpu frequency is 150 mhz for commercial temperature devices and 175 mhz for extended temperature devices. the minimum cpm frequency is 120 mhz. 2 pci_modck determines the pci clock frequency range. see table 20 for lower range configurations. 3 modck_h = hard reset configuration word [28?31] (see section 5.4 in the soc reference manual). modck[1-3] = three hardware configuration pins. 4 cpm multiplication factor = cpm clock/bus clock 5 cpu multiplication factor = core pll multiplication factor table 19. clock configurations for pci agent mode (pci_modck=0) 1,2 (continued) mode 3 pci clock (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) bus division factor bus clock (mhz) modck_h- modck[1-3] low high low high low high low high
mpc8272 powerquicc ii family hardware specifications, rev. 3 40 freescale semiconductor clock configuration modes table 20. clock configurations for pci agent mode (pci_modck=1) 1,2 mode 3 pci clock (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) bus division factor bus clock (mhz) modck_h- modck[1-3] low high low high low high low high default modes (modck_h=0000) 0000_000 30.0 50.0 4 120.0 200.0 2.5 150.0 250.0 2 60.0 100.0 0000_001 25.0 50.0 4 100.0 200.0 3 150.0 300.0 2 50.0 100.0 0000_010 25.0 50.0 6 150.0 300.0 3 150.0 300.0 3 50.0 100.0 0000_011 25.0 50.0 6 150.0 300.0 4 200.0 400.0 3 50.0 100.0 0000_100 25.0 50.0 6 150.0 300.0 3 180.0 360.0 2.5 60.0 120.0 0000_101 25.0 50.0 6 150.0 300.0 3.5 210.0 420.0 2.5 60.0 120.0 0000_110 25.0 50.0 8 200.0 400.0 3.5 233.3 466.7 3 66.7 133.3 0000_111 25.0 50.0 8 200.0 400.0 3 240.0 480.0 2.5 80.0 160.0 full configuration modes 0001_001 30.0 50.0 4 120.0 200.0 5 150.0 250.0 4 30.0 50.0 0001_010 25.0 50.0 4 100.0 200.0 6 150.0 300.0 4 25.0 50.0 0001_011 25.0 50.0 4 100.0 200.0 7 175.0 350.0 4 25.0 50.0 0001_100 25.0 50.0 4 100.0 200.0 8 200.0 400.0 4 25.0 50.0 0010_001 25.0 50.0 6 150.0 300.0 3 180.0 360.0 2.5 60.0 120.0 0010_010 25.0 50.0 6 150.0 300.0 3.5 210.0 420.0 2.5 60.0 120.0 0010_011 25.0 50.0 6 150.0 300.0 4 240.0 480.0 2.5 60.0 120.0 0010_100 25.0 50.0 6 150.0 300.0 4.5 270.0 540.0 2.5 60.0 120.0 0011_000 reserved 0011_001 37.5 50.0 4 150.0 200.0 3 150.0 200.0 3 50.0 66.7 0011_010 32.1 50.0 4 128.6 200.0 3.5 150.0 233.3 3 42.9 66.7 0011_011 28.1 50.0 4 112.5 200.0 4 150.0 266.7 3 37.5 66.7 0011_100 25.0 50.0 4 100.0 200.0 4.5 150.0 300.0 3 33.3 66.7 0100_000 reserved 0100_001 25.0 50.0 6 150.0 300.0 3 150.0 300.0 3 50.0 100.0 0100_010 25.0 50.0 6 150.0 300.0 3.5 175.0 350.0 3 50.0 100.0 0100_011 25.0 50.0 6 150.0 300.0 4 200.0 400.0 3 50.0 100.0
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 41 clock configuration modes 0100_100 25.0 50.0 6 150.0 300.0 4.5 225.0 450.0 3 50.0 100.0 0101_000 30.0 50.0 5 150.0 250.0 2.5 150.0 250.0 2.5 60.0 100.0 0101_001 25.0 50.0 5 125.0 250.0 3 150.0 300.0 2.5 50.0 100.0 0101_010 25.0 50.0 5 125.0 250.0 3.5 175.0 350.0 2.5 50.0 100.0 0101_011 25.0 50.0 5 125.0 250.0 4 200.0 400.0 2.5 50.0 100.0 0101_100 25.0 50.0 5 125.0 250.0 4.5 225.0 450.0 2.5 50.0 100.0 0101_101 25.0 50.0 5 125.0 250.0 5 250.0 500.0 2.5 50.0 100.0 0101_110 25.0 50.0 5 125.0 250.0 5.5 275.0 550.0 2.5 50.0 100.0 0110_000 reserved 0110_001 25.0 50.0 8 200.0 400.0 3 200.0 400.0 3 66.7 133.3 0110_010 25.0 50.0 8 200.0 400.0 3.5 233.3 466.7 3 66.7 133.3 0110_011 25.0 50.0 8 200.0 400.0 4 266.7 533.3 3 66.7 133.3 0110_100 25.0 50.0 8 200.0 400.0 4.5 300.0 600.0 3 66.7 133.3 0111_000 25.0 50.0 6 150.0 300.0 2 150.0 300.0 2 75.0 150.0 0111_001 25.0 50.0 6 150.0 300.0 2.5 187.5 375.0 2 75.0 150.0 0111_010 25.0 50.0 6 150.0 300.0 3 225.0 450.0 2 75.0 150.0 0111_011 25.0 50.0 6 150.0 300.0 3.5 262.5 525.0 2 75.0 150.0 1000_000 reserved 1000_001 25.0 50.0 6 150.0 300.0 2.5 150.0 300.0 2.5 60.0 120.0 1000_010 25.0 50.0 6 150.0 300.0 3 180.0 360.0 2.5 60.0 120.0 1000_011 25.0 50.0 6 150.0 300.0 3.5 210.0 420.0 2.5 60.0 120.0 1000_100 25.0 50.0 6 150.0 300.0 4 240.0 480.0 2.5 60.0 120.0 1000_101 25.0 50.0 6 150.0 300.0 4.5 270.0 540.0 2.5 60.0 120.0 1001_000 reserved 1001_001 reserved table 20. clock configurations for pci agent mode (pci_modck=1) 1,2 (continued) mode 3 pci clock (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) bus division factor bus clock (mhz) modck_h- modck[1-3] low high low high low high low high
mpc8272 powerquicc ii family hardware specifications, rev. 3 42 freescale semiconductor clock configuration modes 1001_010 reserved 1001_011 25.0 50.0 8 200.0 400.0 4 200.0 400.0 4 50.0 100.0 1001_100 25.0 50.0 8 200.0 400.0 4.5 225.0 450.0 4 50.0 100.0 1010_000 reserved 1010_001 25.0 50.0 8 200.0 400.0 3 200.0 400.0 3 66.7 133.3 1010_010 25.0 50.0 8 200.0 400.0 3.5 233.3 466.7 3 66.7 133.3 1010_011 25.0 50.0 8 200.0 400.0 4 266.7 533.3 3 66.7 133.3 1010_100 25.0 50.0 8 200.0 400.0 4.5 300.0 600.0 3 66.7 133.3 1011_000 reserved 1011_001 25.0 50.0 8 200.0 400.0 2.5 200.0 400.0 2.5 80.0 160.0 1011_010 25.0 50.0 8 200.0 400.0 3 240.0 480.0 2.5 80.0 160.0 1011_011 25.0 50.0 8 200.0 400.0 3.5 280.0 560.0 2.5 80.0 160.0 1011_100 25.0 50.0 8 200.0 400.0 4 320.0 640.0 2.5 80.0 160.0 1011_101 25.0 50.0 8 200.0 400.0 2.5 250.0 500.0 2 100.0 200.0 1011_110 25.0 50.0 8 200.0 400.0 3 300.0 600.0 2 100.0 200.0 1011_111 25.0 50.0 8 200.0 400.0 3.5 350.0 700.0 2 100.0 200.0 1100_101 25.0 50.0 6 150.0 300.0 4 200.0 400.0 3 50.0 100.0 1100_110 25.0 50.0 6 150.0 300.0 4.5 225.0 450.0 3 50.0 100.0 1100_111 25.0 50.0 6 150.0 300.0 5 250.0 500.0 3 50.0 100.0 1101_000 25.0 50.0 6 150.0 300.0 5.5 275.0 550.0 3 50.0 100.0 1101_001 25.0 50.0 6 150.0 300.0 3.5 210.0 420.0 2.5 60.0 120.0 1101_010 25.0 50.0 6 150.0 300.0 4 240.0 480.0 2.5 60.0 120.0 1101_011 25.0 50.0 6 150.0 300.0 4.5 270.0 540.0 2.5 60.0 120.0 1101_100 25.0 50.0 6 150.0 300.0 5 300.0 600.0 2.5 60.0 120.0 table 20. clock configurations for pci agent mode (pci_modck=1) 1,2 (continued) mode 3 pci clock (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) bus division factor bus clock (mhz) modck_h- modck[1-3] low high low high low high low high
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 43 pinout 8 pinout this figure and table show the pin assignments and pinout for the 516 pbga package. 1110_000 25.0 50.0 5 125.0 250.0 2.5 156.3 312.5 2 62.5 125.0 1110_001 25.0 50.0 5 125.0 250.0 3 187.5 375.0 2 62.5 125.0 1110_010 28.6 50.0 5 142.9 250.0 3.5 250.0 437.5 2 71.4 125.0 1110_011 25.0 50.0 5 125.0 250.0 4 250.0 500.0 2 62.5 125.0 1110_100 25.0 50.0 5 125.0 250.0 4 166.7 333.3 3 41.7 83.3 1110_101 25.0 50.0 5 125.0 250.0 4.5 187.5 375.0 3 41.7 83.3 1110_110 25.0 50.0 5 125.0 250.0 5 208.3 416.7 3 41.7 83.3 1110_111 25.0 50.0 5 125.0 250.0 5.5 229.2 458.3 3 41.7 83.3 1100_000 reserved 1100_001 reserved 1100_010 reserved 1 the ?low? values are the minimum allowable frequencies for a given clock mode. the minimum bus frequency in a table entry guarantees only the required minimum cpu operating frequency. the ?high? values are for the purpose of illustration only. users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user?s device. the minimum cpu frequency is 150 mhz for commercial temperature devices and 175 mhz for extended temperature devices. the minimum cpm frequency is 120 mhz. 2 pci_modck determines the pci clock frequency range. see table 19 for higher range configurations. 3 modck_h = hard reset configuration word [28?31] (see section 5.4 in the soc reference manual). modck[1-3] = three hardware configuration pins. 4 cpm multiplication factor = cpm clock/bus clock 5 cpu multiplication factor = core pll multiplication factor table 20. clock configurations for pci agent mode (pci_modck=1) 1,2 (continued) mode 3 pci clock (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) bus division factor bus clock (mhz) modck_h- modck[1-3] low high low high low high low high
mpc8272 powerquicc ii family hardware specifications, rev. 3 44 freescale semiconductor pinout this figure shows the pinout of the 516 pbga package as viewed from the top surface. figure 12. pinout of the 516 pbga package (view from top) this table lists the pins of the mpc8272. note that the pins in the ?mpc8272/8271 only? column relate to utopia functionality. table 21. pinout pin name ball mpc8272/mpc8248 and mpc8271/mpc8247 mpc8272/mpc8271 only br a19 bg /irq6 d2 abb /irq2 c1 12345678910111213141516 17 18 19 20 21 22 23 24 25 26 not to scale 1234567891011121314151617181920212223242526 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 45 pinout ts d1 a0 a3 a1 b5 a2 d8 a3 c6 a4 a4 a5 a6 a6 b6 a7 c7 a8 b7 a9 a7 a10 d9 a11 e11 a12 c9 a13 b9 a14 d11 a15 a9 a16 b10 a17 a10 a18 b11 a19 a11 a20 d12 a21 a12 a22 d13 a23 b13 a24 c13 a25 c14 a26 b14 a27 d14 a28 e14 a29 a14 table 21. pinout (continued) pin name ball mpc8272/mpc8248 and mpc8271/mpc8247 mpc8272/mpc8271 only
mpc8272 powerquicc ii family hardware specifications, rev. 3 46 freescale semiconductor pinout a30 b15 a31 a15 tt0 b3 tt1 e8 tt2 d7 tt3 c4 tt4 e7 tbst e3 tsiz0 e4 tsiz1 e5 tsiz2 c3 tsiz3 d5 aack d3 artry c2 dbg /irq7 f16 dbb /irq3 d18 d0 ac1 d1 aa1 d2 v3 d3 r5 d4 p4 d5 m4 d6 j4 d7 g1 d8 w6 d9 y3 d10 v1 d11 n6 d12 p3 d13 m2 d14 j5 table 21. pinout (continued) pin name ball mpc8272/mpc8248 and mpc8271/mpc8247 mpc8272/mpc8271 only
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 47 pinout d15 g3 d16 ab3 d17 y1 d18 t4 d19 t3 d20 p2 d21 m1 d22 j1 d23 g4 d24 ab2 d25 w4 d26 v2 d27 t1 d28 n5 d29 l1 d30 h1 d31 g5 d32 w5 d33 w2 d34 t5 d35 t2 d36 n1 d37 k3 d38 h2 d39 f1 d40 aa2 d41 w1 d42 u3 d43 r2 d44 n2 d45 l2 table 21. pinout (continued) pin name ball mpc8272/mpc8248 and mpc8271/mpc8247 mpc8272/mpc8271 only
mpc8272 powerquicc ii family hardware specifications, rev. 3 48 freescale semiconductor pinout d46 h4 d47 f2 d48 ab1 d49 u4 d50 u1 d51 r3 d52 n3 d53 k2 d54 h5 d55 f4 d56 aa3 d57 u5 d58 u2 d59 p5 d60 m3 d61 k4 d62 h3 d63 e1 irq3 /ckstp_out /ext_br3 b16 irq4 /core_sreset /ext_bg3 c15 irq5 /tben /ext_dbg3 /cint y4 psdval c19 ta aa4 tea ab6 gbl /irq1 d15 ci /baddr29/irq2 d16 wt /baddr30/irq3 c16 baddr31/irq5 /cint e17 cpu_br /int_out b20 cs0 ae6 cs1 ad7 table 21. pinout (continued) pin name ball mpc8272/mpc8248 and mpc8271/mpc8247 mpc8272/mpc8271 only
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 49 pinout cs2 af5 cs3 ac8 cs4 af6 cs5 ad8 cs6 /bctl1 /smi ac9 cs7 /tlbisync ab9 baddr27/irq1 ab8 baddr28/irq2 ac7 ale/irq4 af4 bctl0 af3 pwe0 /psddqm0 /pbs0 ad6 pwe1 /psddqm1 /pbs1 ae5 pwe2 /psddqm2 /pbs2 ae3 pwe3 /psddqm3 /pbs3 af2 pwe4 /psddqm4 /pbs4 ac6 pwe5 /psddqm5 /pbs5 ac5 pwe6 /psddqm6 /pbs6 ad4 pwe7 /psddqm7 /pbs7 ab5 psda10/pgpl0 ae2 psdwe /pgpl1 ad3 poe /psdras /pgpl2 ab4 psdcas /pgpl3 ac3 pgta /pupmwait/pgpl4 ad2 psdamux/pgpl5 ac2 pci_mode 1 ad22 pci_cfg0 (pci_host_en )ac21 pci_cfg1 (pci_arb_en) ae22 pci_cfg2 (dll_enable) ae23 pci_ par af12 pci_frame ad15 pci_trdy af16 table 21. pinout (continued) pin name ball mpc8272/mpc8248 and mpc8271/mpc8247 mpc8272/mpc8271 only
mpc8272 powerquicc ii family hardware specifications, rev. 3 50 freescale semiconductor pinout pci_irdy af15 pci_stop ae15 pci_devsel ae14 pci_idsel ac17 pci_perr ad14 pci_serr ad13 pci_req0 ae20 pci_req1 /cpci_hs_es af14 pci_gnt0 ad20 pci_gnt1 /cpci_hs_led ae13 pci_gnt2 /cpci_hs_enum af21 pci_rst af22 pci_inta ae21 pci_req2 ab14 dllout ac22 pci_ad0 af7 pci_ad1 ae10 pci_ad2 ab10 pci_ad3 ad10 pci_ad4 ae9 pci_ad5 af8 pci_ad6 ac10 pci_ad7 ae11 pci_ad8 ab11 pci_ad9 af10 pci_ad10 af9 pci_ad11 ab12 pci_ad12 ac12 pci_ad13 ad12 pci_ad14 af11 pci_ad15 ab13 table 21. pinout (continued) pin name ball mpc8272/mpc8248 and mpc8271/mpc8247 mpc8272/mpc8271 only
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 51 pinout pci_ad16 ae16 pci_ad17 af17 pci_ad18 ad16 pci_ad19 ac16 pci_ad20 af18 pci_ad21 ab16 pci_ad22 ad17 pci_ad23 af19 pci_ad24 ab17 pci_ad25 af20 pci_ad26 ae19 pci_ad27 ac18 pci_ad28 ab18 pci_ad29 ad19 pci_ad30 ad21 pci_ad31 ac20 pci_c0 /be0 ae12 pci_c1 /be1 af13 pci_c2 /be2 ac15 pci_c3 /be3 ae18 irq0 /nmi_out a17 trst 2 e21 tck b22 tms c23 tdi b24 tdo a22 tris b23 poreset 2 /pci_rst c24 hreset d22 sreset f22 rstconf a24 table 21. pinout (continued) pin name ball mpc8272/mpc8248 and mpc8271/mpc8247 mpc8272/mpc8271 only
mpc8272 powerquicc ii family hardware specifications, rev. 3 52 freescale semiconductor pinout modck1/rsrv /tc0/bnksel0 a20 modck2/cse0/tc1/bnksel1 c20 modck3/cse1/tc2/bnksel2 a21 clkin1 d21 pa8/smrxd2 af25 3 pa9/smtxd2 aa22 3 pa10/msnum5 fcc1_ut_rxd0 ab23 3 pa11/msnum4 fcc1_ut_rxd1 ad26 3 pa12/msnum3 fcc1_ut_rxd2 ad25 3 pa13/msnum2 fcc1_ut_rxd3 aa24 3 pa14/fcc1_mii_hdlc_rxd3 fcc1_ut_rxd4 w22 3 pa15/fcc1_mii_hdlc_rxd2 fcc1_ut_rxd5 y24 3 pa16/fcc1_mii_hdlc_rxd1 fcc1_ut_rxd6 t22 3 pa17/fcc1_mii_hdlc_rxd0/ fcc1_mii_tran_rxd/fcc1_rmii_rx d0 fcc1_ut_rxd7 w26 3 pa18/fcc1_mii_hdlc_txd0/fcc1_mii _tran_txd/ fcc1_rmii_txd0 fcc1_ut_txd7 v26 3 pa19/fcc1_mii_hdlc_txd1/fcc1_rm ii_txd1 fcc1_ut_txd6 r23 3 pa20/fcc1_mii_hdlc_txd2 fcc1_ut_txd5 p25 3 pa21/fcc1_mii_hdlc_txd3 fcc1_ut_txd4 n22 3 pa22 fcc1_ut_txd3 n26 3 pa23 fcc1_ut_txd2 n23 3 pa24/msnum1 fcc1_ut_txd1 h26 3 pa25/msnum0 fcc1_ut_txd0 g25 3 pa26/fcc1_mii_rmiirx_er fcc1_ut_rxclav l22 3 pa27/fcc1_mii_rx_dv/fcc1_rmii_cr s_dv fcc1_ut_rxsoc g24 3 pa28/fcc1_mii_rmii_tx_en fcc1_ut_rxenb g23 3 pa29/fcc1_mii_tx_er fcc1_ut_txsoc b26 3 pa30/fcc1_mii_crs/fcc1_rts fcc1_ut_txclav a25 3 table 21. pinout (continued) pin name ball mpc8272/mpc8248 and mpc8271/mpc8247 mpc8272/mpc8271 only
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 53 pinout pa31/fcc1_mii_col fcc1_ut_txenb g22 3 pb18/fcc2_mii_hdlc_rxd3 t25 3 pb19/fcc2_mii_hdlc_rxd2 p22 3 pb20/fcc2_mii_hdlc_rmii_rxd1 l25 3 pb21/fcc2_mii_hdlc_rmii_rxd0/fcc2_tran_rxd j26 3 pb22/fcc2_mii_hdlc_txd0/fcc2_tran_txd/ fcc2_rmii_txd0 u23 3 pb23/fcc2_mii_hdlc_txd1/fcc2_rmii_txd1 u26 3 pb24/fcc2_mii_hdlc_txd2/l1rsyncb2 m24 3 pb25/fcc2_mii_hdlc_txd3/l1tsyncb2 m23 3 pb26/fcc2_mii_crs/l1rxdb2 h24 3 pb27/fcc2_mii_col/l1txdb2 e25 3 pb28/fcc2_mii_rmii_rx_er/fcc2_rts /txd1 d26 3 pb29/fcc2_mii_rmii_tx_en k21 3 pb30/fcc2_mii_rx_dv/fcc2_rmii_crs_dv d24 3 pb31/fcc2_mii_tx_er e23 3 pc0/dreq3 /brgo7/smsyn1 /l1clkoa2 af23 3 pc1/brgo6/l1rqa2 ad23 3 pc4/smrxd1/si2_l1st4/fcc2_cd ab22 3 pc5/smtxd1/si2_l1st3/fcc2_cts ae24 3 pc6/fcc1_cd /si2_l1st2 fcc1_ut_rxaddr2 af24 3 pc7/fcc1_cts fcc1_ut_txaddr2 ae26 3 pc8/cd4 /rts1/si2_l1st2/cts3 ac24 3 pc9/cts4 /l1tsynca2 aa23 3 pc10/cd3 /usb_rn ab25 3 pc11/cts3 /usb_rp/l1txd3a2 v22 3 pc12 fcc1_ut_rxaddr1 aa26 3 pc13/brgo5 fcc1_ut_txaddr1 v23 3 pc14/cd1 fcc1_ut_rxaddr0 w24 3 pc15/cts1 fcc1_ut_txaddr0 u24 3 pc16/clk16 t23 3 table 21. pinout (continued) pin name ball mpc8272/mpc8248 and mpc8271/mpc8247 mpc8272/mpc8271 only
mpc8272 powerquicc ii family hardware specifications, rev. 3 54 freescale semiconductor pinout pc17/clk15/brgo8/done2 t26 3 pc18/clk14/tgate2 r26 3 pc19/clk13/brgo7/tgate1 p24 3 pc20/clk12/usboe l26 3 pc21/clk11/brgo6/cp_int l24 3 pc22/clk10/done3 fcc1_ut_txprty l23 3 pc23/clk9/brgo5/dack3 /cd1 k24 3 pc24/clk8/tin3/tout4 /dreq2/brgo1 k23 3 pc25/clk7/brgo4/dack2 /spisel f26 3 pc26/clk6/tout3 /tmclk h23 3 pc27/clk5/brgo3/tout1 fcc1_ut_rxprty k22 3 pc28/clk4/tin1/tout2 /spiclk d25 3 pc29/clk3/tin2/brgo2/cts1 f24 3 pd7/smsyn2 fcc1_ut_txaddr3 ab21 3 pd14/i2cscl ac26 3 pd15/i2csda y23 3 pd16/spimiso fcc1_ut_txprty aa25 3 pd17/brgo2/spimosi fcc1_ut_rxprty y26 3 pd18/spiclk fcc1_ut_rxaddr4 w25 3 pd19/spisel/brgo1 fcc1_ut_txaddr4 v25 3 pd20/rts4 /l1rsynca2 r24 3 pd21/txd4/l1rxd0a2 p23 3 pd22/rxd4/l1txd0a2 n25 3 pd23/rts3 /usb_tp k26 3 pd24/txd3/usb_tn k25 3 pd25/rxd3/usb_rxd j25 3 pd29/rts1 fcc1_ut_rxaddr3 c26 3 pd30/txd1 e24 3 pd31/rxd1 b25 3 vccsyn c18 vccsyn1 k6 table 21. pinout (continued) pin name ball mpc8272/mpc8248 and mpc8271/mpc8247 mpc8272/mpc8271 only
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 55 pinout clkin2 c21 no connect 4 d19 4 , j3 4 , ad24 5 i/o power b4, f3, j2, n4, ad1, ad5, ae8, ac13, ad18, ab24, ab26, w23, r25, m25, f25, c25, c22, b17, b12, b8, e6, f6, h6, l5, l6, p6, t6, u6, v5, y5, aa6, aa8, aa10, aa11, aa14, aa16, aa17, ab19, ab20, w21, u21, t21, p21, n21, m22, j22, h21, f21, f19, f17, e16, f14, e13, e12, f10, e10, e9 core power f5, k5, m5, aa5, ab7, aa13, aa19, aa21, y22, ac25, u22, r22, l21, h22, e22, e20, e15, f13, f11, f8, l3, v4, w3, ac11, ad11, ab15, u25, t24, j24, h25, f23, b19, d17, c17, d10, c10 ground e19, e2, k1, y2, ae1, ae4, ad9, ac14, ae17, ac19, ae25, v24, p26, m26, g26, e26, b21, c12, c11, c8, a8, b18, a18, a2, b1, b2, a5, c5, d4, d6, g2, l4, p1, r1, r4, ac4, ae7, ac23, y25, n24, j23, a23, d23, d20, e18, a13, a16, k10, k11, k12, k13, k14, k15, k16, k17, l10, l11, l12, l13, l14, l15, l16, l17, m10, m11, m12, m13, m14, m15, m16, m17, n10, n11, n12, n13, n14, n15, n16, n17, p10, p11, p12, p13, p14, p15, p16, p17, r10, r11,r12, r13, r14, r15, r16, r17, t10, t11, t12, t13, t14, t15, t16, t17, u10, u11, u12, u13, u14, u15, u16, u17 1 must be tied to ground. 2 should be tied to vddh via a 2k external pull-up resistor. 3 the default configuration of the cpm pins (pa[8?31], pb[18?31], pc[0?1,4?29], pd[7?25, 29?31]) is input. to prevent excessive dc current, it is recommended either to pull unused pins to gnd or vddh, or to configure them as outputs. 4 this pin is not connected. it should be left floating. 5 must be pulled down or left floating table 21. pinout (continued) pin name ball mpc8272/mpc8248 and mpc8271/mpc8247 mpc8272/mpc8271 only
mpc8272 powerquicc ii family hardware specifications, rev. 3 56 freescale semiconductor package description 9 package description this figure shows the side profile of the pbga package to indicate the direction of the top surface view. figure 13. side view of the pbga package remove 9.1 package parameters this table provides package parameters. note: temperature reflow for the vr package in the vr package, sphere composition is lead-free (see table 2 ). this requires higher temperature reflow than what is required for other powerquicc ii packages. consult ?freescale powerquicc ii pb-free packaging information? (mpc8250pbfreepkg) available on www.freescale.com. table 22. package parameters code type outline (mm) interconnects pitch (mm) nominal unmounted height (mm) vr, zq pbga 27 x 27 516 1 2.25 die transfer molding compound 1 mm pitch wire bonds attach die ball bond screen-printed solder mask cu substrate traces resin glass epoxy plated substrate via
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 57 package description 9.2 mechanical dimensions this figure provides the mechanical dimensions and bottom surface nomenclature of the 516 pbga package. figure 14. mechanical dimensions and bottom surface nomenclature?516 pbga
mpc8272 powerquicc ii family hardware specifications, rev. 3 58 freescale semiconductor ordering information 10 ordering information this figure provides an example of the freescale part numbering nomenclature for the soc. in addition to the processor frequency, the part numbering scheme also consists of a part modifier that indicates any enhancement(s) in the part from the original producti on design. each part number also contains a revision code that refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. for more information, contact your local freescale sales office. figure 15. freescale part number key 11 document revision history this table summarizes changes to this document. table 23. document revision history revision date substantive changes 3 09/2011 in figure 15 , ?freescale part number key,? added speed decoding information below processor frequency information. 2 12/2008 ? modified figure 5 , ?scc/smc/spi/i2c external clock diagram,? and added second section of figure notes. ?in ta b l e 1 2 , modified ?data bus in pipeline mode? row and showed 66 mhz as ?n/a.? ?in section 10, ?ordering information ,? added ?f = 133? to cpu/cpm/bus frequency. ? added footnote concerning cpm_clk/pci_clk ratio to column ?pci division factor? in ta ble 1 7 , ?clock configurations for pci host mode (pci_modck=0),? and ta b l e 1 8 , ?clock configurations for pci host mode (pci_modck=1),.? ? removed overbar from dll_enable in ta b l e 2 1 , ?pinout.? 1.5 12/2006 ? section 6, ?ac electrical characteristics,? removed deratings statement and clarified ac timing descriptions. 1.4 05/2006 ? added row for 133 mhz configurations to table 8 . 1.3 02/2006 ? inserted section 6.3, ?jtag timings.? product code device number package die revision level mpc 82xx c vr xxx x temperature range blank = 0 to 105 c c = ?40 to 105 c zq = 516 pbga (lead spheres) vr = 516 pbga (no lead spheres) b = 66 e = 100 f = 133 i = 200 m = 266 p = 300 t = 400 processor frequency cpu/cpm/bus in mhz)
mpc8272 powerquicc ii family hardware specifications, rev. 3 freescale semiconductor 59 document revision history 1.2 09/2005 ? added 133-mhz to the list of frequencies in the opening sentence of section 6, ?ac electrical characteristics?. ? added 133 mhz columns to ta b l e 9 , table 11 , ta ble 1 2 , and ta b l e 1 3 . ? added footnote 2 to ta ble 1 3 . ? added the conditions note directly above ta b l e 1 2 . 1.1 01/2005 ? modification for correct display of assertion level (?overbar ?) for some signals 1.0 12/2004 ? section 1.1: added 8:1 ratio to internal cpm/bus clock multiplier values ? section 2: removed voltage tracking note ? ta ble 3 : note 2 updated regarding vdd/vccsyn relationship to vddh during power-on reset ? ta ble 4 : updated vdd and vccsyn to 1.425 v - 1.575 v ? ta ble 8 : note 2 updated to reflect vih=2.5 for tck, trst, poreset; request for external pull-up removed. ? section 4.6: updated description of layout practices ? ta ble 8 : note 3 added regarding iic compatibility ? ta ble 8 : updated nominal and maximum power dissipation values ? ta ble 9 : updated pci impedance to 27 , updated 60x and memc values and added note to reflect configurable impedance ? section 6: added sentence providing derating factor ? section 6.1: added note: rise/fall time on cpm input pins ? ta ble 9 : updated values for following specs: sp36b, sp37a, sp38a, sp39a, sp38b, sp40, sp41, sp42, sp43, sp42a ? ta ble 1 1 : updated values for following specs: sp16a, sp16b, sp18a, sp18b, sp20, sp21, sp22 ? section 6.2: added spread spectrum clocking note ? section 6.2: added clkin jitter note ? ta ble 1 2 : combined specs sp11 and sp11a ? ta ble 1 3 : sp30 data bus minimum delay values changed to 0.8 ? section 7: unit of ns added to tval notes ? section 7: updated all notes to reflect updated cpu fmin of 150 mhz commercial temp devices, 175 mhz extended temp; cpm fmin of 120 mhz. ? section 7, ?clock configuration modes ?: updated all table footnotes reflect updated cpu fmin of 150 mhz commercial temp devices, 175 mhz extended temp; cpm fmin of 120 mhz. ? ta ble 2 1 : correct superscript of footnote number after pin ad22 ? ta ble 2 1 : remove done3 from pc12 ? ta ble 2 1 : signals referring to tdms c2 and d2 removed table 23. document revision history (continued) revision date substantive changes
mpc8272 powerquicc ii family hardware specifications, rev. 3 60 freescale semiconductor document revision history 0.2 12/2003 ? ta ble 1 : new ? ta ble 2 : new ? ta ble 4 : modification of vdd and vccsyn to 1.45?1.60 v ? ta ble 8 : addition of note 2 regarding trst and poreset (see v ih row of ta b l e 8 ) ? ta ble 8 and tab le 2 1 : addition of muxed signals cpci_hs_es to pci_req1 (af14) cpci_hs_led to pci_gnt1 (ae13) cpci_hs_enum to pci_gnt2 (af21) ? ta ble 8 and ta b l e 2 1 : modification of pci signal names for consistency with pci signal names on other powerquicc ii devices: pci_cfg0 (pci_host_en ) (ac21) pci_cfg1 (pci_arb_en ) (ae22) pci_cfg2 (dll_enable) (ae23) pci_par (af12) pci_frame (ad15) pci_trdy (af16) pci_irdy (af15) pci_stop (ae15) devsel (ae14) pci_idsel (ac17) pci_perr (ad14) pci_serr (ad13) pci_req0?2 (aae20, af14, ab14) pci_gnt0?2 (ad20, ae13, af21) pci_rst (af22) pci_inta (ae21) pci_c0-3 (ae12, af13, ac15, ae18) pci_ad0-31 ? ta ble 8 and tab le 2 1 : corrected assertion level (added ? ?) pci_host_en (ac21) and pci_arb_en (ae22) ? ta ble 7 : addition of r jt and note 4 ? sections 4.1?4.5 and 4.7 on thermal characteristics: new ? section 7, ?clock configuration modes ?: modification to first paragraph. note that pci_modck is a bit in the hard reset configuration word. it is not an input signal as it is in the mpc8280 family and mpc8260 family. ? addition of ?note: temperature reflow for the vr package" on page 56 ? ta ble 2 1 : addition of note 2 to trst (e21) and poreset (c24) ? ta ble 2 1 : removal of thermal0 (d19) and thermal1(j3). these pins are now ?no connects.? note 4 unchanged. ? ta ble 2 1 : removal of spare0 (ad24). this pin is now a ?no connect.? note 5 unchanged. ? ta ble 2 1 : addition of pci_mode (ad22). this pin was previously listed as ?ground.? addition of note 1. 0.1 9/2003 ? addition of the mpc8271 and the mpc8247 (these devices do not have a security engine) ? ta ble 8 : addition of note 2 to v ih ? ta ble 8 : changed i ol for 60x signals to 6.0 ma ? modification of note 1 for ta b l e 1 7 , ta b l e 1 8 , tab le 1 9 , and ta ble 2 0 ? ta ble 2 1 : addition of ball ad9 to gnd. in rev 0 of this document, ad8 was listed as assigned to both cs5 and gnd. ad8 is only assigned to cs5 . ? ta ble 2 1 : addition of note 4 to thermal0 (d19) and thermal1(j3) ? addition of zq package code to figure 15 0 5/2003 nda release table 23. document revision history (continued) revision date substantive changes
document number: mpc8272ec rev. 3 09/2011 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center 1-800 441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com freescale, the freescale logo, codewarrior, coldfire, powerquicc, qoriq, starcore, and symphony are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. corenet, qoriq qonverge, quicc engine, and vortiqa are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. ? 2002?2011 freescale semiconductor, inc.

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